Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

15.4. Clocked Video Output IP Interfaces

The IP has up to three video input interfaces:

  • An AXI4-S video input for the primary pixel data input, axi4s_vid_in
  • An optional AXI4-S video Input for the test pattern generator pixel data input, axi4s_tpg_in
  • An optional AXI4-S full-raster input for the real-time video raster data, axi4s_fr_timing_in

The IP has one video output interface, an AXI4-S full-raster bus, axi4s_fr_vid_out

The IP has one optional CPU interface, av_mm_cpu_agent

The CPU interface is asynchronous to the video output interface. Assume the video clock can be unstable when you select a new standard, which can cause unreliable behavior if used for the CPU interface.

The proprietary Intel FPGA streaming full-raster protocol is compatible with AMBA AXI4-stream interfaces to connect components that exchange video data. The protocols allow interfaces to Intel FPGA video IPs or other AXI4-Stream compliant third-party video IPs. Table 4 provides a description for each of the conduits on the output and input interfaces.

The video clock and CPU clock are assumed to be asynchronous to each other. Internally, the Clocked Video Output IP includes clock domain crossing (CDC) circuits for both single bit and data bus signal cases, which allows safe data exchange between the two asynchronous clock domains. The Clocked Video Output IP also includes an embedded entity .sdc file, which provides all the necessary information to the Timing Analyzer. For system integration, when you instantiate the Clocked Video Output IP in a design, the only constraints required are:

  • Clock frequency constraints for the timing reference input clock (fr_clock_clk)
  • Clock frequency constraints for the primary video clock (vid_clock_clk)
  • Clock frequency constraints for the test pattern input video clock (tpg_clock_clk)
  • Clock frequency constraints for the CPU clock (cpu_clock_clk)
Table 196.  Clocked Video Output IP InterfacesThe table shows a description for each of the conduits on the output and input interfaces
Signal name Direction Width Description
Clocks and resets
vid_clock_clk Input 1 Input AXI4-S video main video input processing clock
vid_reset_reset Input 1 Input AXI4-S video main video processing reset
tpg_clock_clk Input 1 Input AXI4-S video test pattern input processing clock
tpg_reset_reset Input 1 Input AXI4-S video test pattern input processing reset
fr_clock_clk Input 1 Processing clock for input and output AXI4-S full-raster interfaces.
fr_reset_reset Input 1 Reset for input and output AXI4-S full-raster interfaces.
cpu_clock_clk Input 1

Processor interface processing clock

cpu_reset_reset Input 1

ProcessoriInterface processing reset

Control Interface

This interface is only available if you turn on CPU support.

av_mm_cpu_agent_address Input 7 Control agent port Avalon memory-mapped address bus. Specifies a word offset into the agent address space.
av_mm_cpu_agent_read Input 1 Control agent port Avalon memory-mapped read signal. When you assert this signal, the control port drives new data onto the read data bus.
av_mm_cpu_agent_read_data_valid Output 1 Control agent port Avalon memory-mapped read data valid signal. The IP asserts this signal on the same clock cycle when the read data is valid.
av_mm_cpu_agent_readdata Output 32 Control agent port Avalon memory-mapped read data bus. These output lines are for read transfers
av_mm_cpu_agent_waitrequest Output 1 Control agent port Avalon memory-mapped wait request bus. This signal indicates that the agent is stalling the master transaction.
av_mm_cpu_agent_write Input 1 Control agent port Avalon memory-mapped write signal. When you assert this signal, the control port accepts new data from the write data bus.
av_mm_cpu_agent_writedata Input 32 Control agent port Avalon memory-mapped write data bus. These input lines are for writing transfers.
av_mm_cpu_agent_byteenable Input 4 Control agent port Avalon memory-mapped byte enable bus. These lines indicate which bytes are selected for write and read transactions.
Intel FPGA streaming video interfaces
axi4s_fr_vid_out_tdata Output 30 31 32 AXI4-S full-raster data out
axi4s_fr_vid_out_tvalid Output 1 AXI4-S data valid
axi4s_fr_vid_out_tuser[0] Output 1 AXI4-S start of video frame
axi4s_fr_vid_out_tlast Output 1 AXI4-S end of packet
axi4s_fr_vid_out_tready Input 1 AXI4-S data ready
axi4s_fr_timing_in_tdata Input 30 31 32 AXI4-S full-raster timing data in
axi4s_fr_timing_in_tvalid Input 1 AXI4-S data valid
axi4s_fr_timing_in_tuser[0] Input 1 AXI4-S start of video frame
axi4s_fr_timing_in_tlast Input 1 AXI4-S end of packet
axi4s_fr_timing_in_tready Output 1 AXI4-S data ready
axi4s_vid_in_tdata Output 30 31 32 AXI4-S data in
axi4s_vid_in_tvalid Output 1 AXI4-S data valid
axi4s_vid_in_tuser[0] Output 1 AXI4-S start of video frame
axi4s_vid_in_tlast Output 1 AXI4-S end of packet
axi4s_vid_in_tready Input 1 AXI4-S data ready
axi4s_tpg_in_tdata Output 30 31 32 AXI4-S data in
axi4s_tpg_in_tvalid Output 1 AXI4-S data valid
axi4s_tpg_in_tuser[0] Output 1 AXI4-S start of video frame
axi4s_tpg_in_tlast Output 1 AXI4-S end of packet
axi4s_tpg_in_tready Input 1 AXI4-S data ready
30

The equation gives all full-raster tdata widths:

max (floor((( bits per color samplex (number of color planes+1) x pixels in parallel) + 7) / 8) x 8, 16)

31

The equation gives all tdata video active only sizes:

max (floor((( bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)

32

The equation gives all tuser widths in these interfaces

N = ceil (tdata width / 8)