Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

22.1. About the Generic Crosspoint IP

The IP is a M x N generic data crosspoint where M and N signify the number of input and output ports, respectively. This IP can route discrete signals around an FPGA design under software control. Both input and output ports work on the same clock domain.
Data is input to and output from the Generic Crosspoint IP via a selectable number of ports. The size of the input and output ports is a global parameter configurable from the GUI. The number of input and output ports is in the range of 1 to 32.
Figure 55. Generic Crosspoint Block Diagram

The front-end and back-end of this IP include a bank of registers, and the crosspoint multiplexer and routing logic, which can process run-time and build-time configurable routing between input and output ports.

You can control the input-to-output routing dynamically at run-time via the CPU interface. You can also assign a default routing at build-time via the Platform Designer IP GUI. The crosspoint routing reverts to the default routing on reset. If you turn off the CPU interface, the crosspoint is statically fixed at the default routing, which you can use if the routing does not need to change at run-time.