Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

1.1. Video and Vision Processing IPs Features

  • Intel FPGA streaming video data interfaces for video I/O, based on the industry-standard AXI4-Stream protocol
  • Avalon memory-mapped agent interfaces for run-time control and Avalon memory-mapped host interface for external memory usage allowing push-button conversion in Intel Platform Designer to industry-standard AXI4 or AXI4-Lite memory-mapped interfaces if required.
  • Device utilization and Fmax on Intel Agilex FPGAs allow 8K60 processing on Intel Agilex platforms with four pixels in parallel at 600 MHz.
  • Processing of 1 to 8 pixels in parallel
  • Support for 1 to 4 color symbols per pixel and RGB and YCbCr 444, 422 and 420 color spaces.
  • Data precision of from 8 to 16 bits per symbol.
  • Video fields with 1 to 16384 pixels in both height and width.