Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

25.3.1. Interlacer IP Interfaces

Table 369.  Interlacer IP Interfaces
Name Direction Width Description
Clocks and resets
main_clock_clk Input 1 AXI4-S processing clock.
main_reset_rst Input 1 AXI4-S processing reset.
agent_clock_clk Input 1 Clock for the Avalon memory-mapped control agent interface. Only if you turn on Separate clock for control interface .
agent_reset_rst Input 1 Reset for the Avalon memory-mapped control agent interface. Only if you turn on Separate clock for control interface .
Control interfaces
av_mm_control_agent_address Input 7 Avalon memory-mapped agent address
av_mm_control_agent_write Input 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata Input 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable Input 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read Input 1 Avalon memory-mapped agent read
av_mm_control_agent_readdata Output 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid Output 1 Avalon memory-mapped agent read
av_mm_control_agent_waitrequest Output 1 Avalon memory-mapped agent wait request

Intel FPGA streaming video interfaces

axi4s_vid_in_tdata Input 66 AXI4-S data in
axi4s_vid_in_tvalid Input 1 AXI4-S data valid
axi4s_vid_in_tuser Input 67

AXI4-S tuser

  • tuser[0]indicates start of video frame when asserted
  • tuser[1] indicates the start of a nonvideo packet when asserted
axi4s_vid_in_tlast Output 1 AXI4-S end of packet
axi4s_vid_in_tready Output 1 AXI4-S data ready
axi4s_vid_out_tdata Output 66 AXI4-S data in
axi4s_vid_out_tvalid Output 1 AXI4-S data valid
axi4s_vid_out_tuser Output 67

AXI4-S tuser

  • tuser[0]indicates start of video frame when asserted
  • tuser[1] indicates the start of a nonvideo packet when asserted
axi4s_vid_out_tlast Output 1 AXI4-S end of packet
axi4s_vid_out_tready Input 1 AXI4-S data ready
66

The equation shows the sizes of all tdata widths in these interfaces:

max (ceil((bits per color sample x number of color planes) / 8) x pixels in parallel x 8, 16)

67

The equation shows the sizes of all tuser widths in these interfaces:

N = ceil (tdata width / 8)