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1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide
37.2. Considering Design Security
When designing the systems based on video and vision processing IPs always conduct a security review of your final design to ensure it meets your security goals.
You can apply these precautions to production or deployed systems. Not all precautions apply to all designs or IPs.
- Remove the JTAG interface from your designs.
- To guarantee video data integrity, restrict access to memory allocated to the frame buffer.
- Control access to areas of memory to prevent unauthorized transactions or corruption by other IPs in the design.
- Ensure that you correctly configure the IP via the I²C interface and that the input video is valid.
- Protect the bitstreams for your design using the security features built-in to Intel Quartus Prime.
- Enable a password for the design’s ARM processor.
- Protect access to your design through development kit ports.
- Restrict debugging access by tools such as Signal Tap.
- Encrypt information on SD cards, FPGA bitstreams, and within DDR memory devices.
- Apply security features to stored video data.
- Consider using an HDCP encryption scheme.
- Consider the boot sequence and boot security aspects of your own design.
- Implement Intel’s FPGA bitstream encryption technology to further protect the FPGA design content of your products. For information on FPGA bitstream encryption technology, refer to Using the Design Security Features in Intel FPGAs.
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