Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

30.2. Switch IP Parameters

The IP offers compile- and run-time parameters.
Table 494.  Switch IP Parameters
Parameter Values Description
Video Data Format
Bits per color sample 8 to 16 Select the number of bits per color sample.
Number of color planes 1 to 4 Select the number of color planes per pixel.
Number of pixels in parallel 1 to 8 Select the number of color planes per pixel.
Switch settings
Number of inputs 1 to 8 Select the number of inputs required
Number of outputs 1 to 8 Select the number of outputs required
Lite mode On or off Turn on for a lite variant of the IP.
All inputs are uninterrupted On or off For lite variants, turn on only when you can ensure that the start of another field follows each end-of-field. If you turn on for lite variants, the switch occurs at the start-of-field, as indicated by TUSER[0]. If you turn off for lite variants, the IP switch occurs at the end-of-field, as indicated by TUSER[0].. Full variants do not use this parameter, as the switch occurs always at field boundaries.
Autoconsume inputs On or off Turn on to allow inputs to consume automatically during switches if required.
Control settings
Debug features On or off No effect. The Switch IP has no debugging features.
Separate clock for control interface On or off Turn on for a separate clock for the control interface
Figure 65. Switch IP GUI

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