Video and Vision Processing Suite Intel® FPGA IP User Guide
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Ixiasoft
Visible to Intel only — GUID: dwj1653493938822
Ixiasoft
9.3. AXI-Stream Broadcaster IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and Resets | |||
vid_clock | In | 1 | AXI4-S processing clock |
vid_reset | In | 1 | AXI4-S processing reset |
Intel FPGA streaming video interfaces | |||
axi4s_vid_in_tdata | In | 6 | AXI4-S data in |
axi4s_vid_in_tvalid | In | 1 | AXI4-S data valid |
axi4s_vid_in_tuser[0] | In | 1 | AXI4-S start of video frame |
axi4s_vid_in_tuser[1] | In | 1 |
|
axi4s_vid_in_tuser[N-1:2] | In | 7 | Unused |
axi4s_vid_in_tlast | In | 1 | AXI4-S end of packet |
axi4s_vid_in_tready | Out | 1 | AXI4-S data ready |
axi4s_vid_out_x_tdata | Out | 6 | AXI4-S data out |
axi4s_vid_out_x_tvalid | Out | 1 | AXI4-S data valid |
axi4s_vid_out_x_tuser[0] | Out | 1 | AXI4-S start of video frame |
axi4s_vid_out_x_tuser[1] | Out | 1 |
|
axi4s_vid_out_x_tuser[N-1:2] | Out | 7 | Unused |
axi4s_vid_out_x_tlast | Out | 1 | AXI4-S end of packet |
axi4s_vid_out_tready | In | 1 | AXI4-S data ready |
The equation gives the TDATA width for these interfaces for full or lite variants:
max (floor(((bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)
The equation gives the TDATA width for these interfaces for full-raster variants:
max (floor(((bits per color sample x (number of color planes + 1) x pixels in parallel) + 7) / 8) x 8, 16)