Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

18.3.5. Result to Output Data Type Conversion

After calculation, the FIR Filter IP converts the fixed-point type of the results to the integer data type of the output.
  1. Scales result. Scaling quickly increases the color depth of the output. You can shift the binary point right –16 to +16 places. The IP implements scaling as a simple shift operation so it does not require multipliers.
  2. Removes fractional bits. If any fractional bits exist, you can choose to remove them through these methods:
    • Truncate to integer. The IP removes fractional bits from the data; equivalent to rounding towards negative infinity.
    • Round half up. The IP rounds up to the nearest integer. If the fractional bits equal 0.5, rounding is towards positive infinity.
    • Round half even. The IP rounds to the nearest integer. If the fractional bits equal 0.5, rounding is towards the nearest even integer.
  3. Convert from signed to unsigned. If any negative numbers exist in the results and the output type is unsigned, you can convert to unsigned through these methods:
    • Saturate to the minimum output value (constraining to range).
    • Replace negative numbers with their absolute positive value.
  4. Constrain to range. If any of the results are beyond a specific range, the IP automatically adds logic to saturate the results to the minimum and maximum output values. The specific range is the specified range of the output guard bands, or if unspecified, the minimum and maximum values allowed by the output bits per pixel.