A newer version of this document is available. Customers should click here to go to the newest version.
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide
30.1. About the Switch IP
The Switch Intel FPGA IP allows connections between video inputs and outputs to provide cross-point switching, multipoint switching, and video broadcast functions.
The switch supports:
- Up to 8 independent video inputs, configurable to block, consume or drive any number of the 1-8 video outputs.
- Up to 8 independent video outputs.
- Clean switching on field boundaries for full variants.
- Configurable switching for lite variants.
- Propagation of auxiliary control packets with their associated field, for full variants.
- 1 to 8 pixels in parallel and any color space.
- Autoconsume inputs
The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The switch IP takes input resolution information from image information packets or from the register interface for lite variants.
An Avalon memory-mapped interface allows the run-time configuration of the switch.
For information about the reset behavior for the switch, refer to Reset Behavior in Video and Vision IPs Dunctional Description.
Switch IP Performance and Resources
Did you find the information on this page useful?