Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

19.2. Frame Cleaner IP Parameters

The IP offers run-time and compile-time parameters.
Parameters Allowed range Description
Video data format
Lite mode on or off Turn on to use the lite variant of the Intel FPGA Streaming Video protocol.
Bits per color sample 8-16 Select the number of bits per color sample.
Number of color planes 1-4 Select the number of color planes per pixel.
Number of pixels in parallel 1-8 Select the number of pixels in parallel at the input and output interfaces.
Protocol settings
Discard auxiliary control packets on or off Turn on to discard all auxiliary control packets (packet types > 1). Not applicable if Lite mode is on.
Custom resolution limits on or off Turn on to apply user-set limits to the minimum and maximum field width and height reported in the outgoing image information packets. Not applicable if Lite mode is on.
Minimum field width 1-65536 Set the minimum output field width.
Maximum field width 1-65536 Set the maximum output field width.
Minimum field height 1-65536 Set the minimum output field height.
Maximum field height 1-65536 Set the maximum output field height.
Control settings
Debug features on or off Turn on for readback of frame info registers (full variant only) and debug information registers via the control agent interface.
Separate clock for control interface on or off Turn on for a separate clock for the control agent interface.
Pipeline optimization
Pipeline ready signals on or off Turn on to add extra pipeline registers to the AXI4-S tready signals.