Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

13.2. Initializing the Clocked Video Input IP

The IP provides an Avalon memory-mapped interface, which you can use as a control interface to configure the IP. Initially, the IP is disabled and does not transmit any data or video. However, the Clocked Video Input IP still detects the format of the clocked video input and accepts data on the input video interface.

To start the output of the IP:

  1. Write a 1 to control register bit 0 to enable the clocked video input block
  2. Write a 1 to control register bit 4 to enable Vsync and Hsync auto-polarity detection.
  3. Optionally, write a 1 to control register bit 3 to enable the frame cleaner logic.
  4. Write the expected output video height and width values to ref_lock_cfg1 register. The IP only starts transmitting video on the output interface when the values on ref_lock_cfg1 matches the values on registers active_line_count and total_line_count.
  5. Write the expected number of frames and output video lines values to ref_lock_cfg2 register. The IP only starts transmitting video on the output interface when the values on ref_lock_cfg2 are matched.
  6. Alternatively, if you write zeros to ref_lock_cfg1 and ref_lock_cfg2, the IP does not try to match any specific output video resolution values and immediately produces video.
  7. Optionally, set the values for each of the color planes that the frame cleaner use to do the padding on the output video frame in case a cable is pulled.
  8. Read status register bit 4. When this bit is 1, the IP starts transmitting video. The transmission starts on the next start of frame boundary.