Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 9/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Generic Crosspoint Intel® FPGA IP x
22.1. About the Generic Crosspoint IP 22.2. Generic Crosspoint IP Parameters 22.3. Generic Crosspoint IP Interfaces 22.4. Generic Crosspoint IP Registers 22.5. Generic Crosspoint IP Software API
22.1. About the Generic Crosspoint IP x
22.1.1. Generic Crosspoint IP Features 22.1.2. Generic Crosspoint Performance and Resources
23. Genlock Signal Router Intel® FPGA IP x
23.1. About the Genlock Signal Router IP 23.2. Genlock Signal Router IP Parameters 23.3. Genlock Signal Router IP Interfaces 23.4. Genlock Signal Router IP Registers 23.5. Genlock Signal Router IP Software API
23.1. About the Genlock Signal Router IP x
23.1.1. Genlock Signal Router IP Features 23.1.2. Genlock Signal Router IP Performance and Resources
24. Guard Bands Intel® FPGA IP x
24.1. About the Guard Bands IP 24.2. Guard Bands IP Parameters 24.3. Guard Bands IP Interfaces 24.4. Guard Bands IP Registers 24.5. Guard Bands IP Software API
24.1. About the Guard Bands IP x
24.1.1. Guard Bands IP Performance and Resources
25. Interlacer Intel® FPGA IP x
25.1. About the Interlacer IP 25.2. Interlacer IP Parameters 25.3. Interlacer IP Functional Description 25.4. Interlacer IP Registers 25.5. Interlacer IP Software API
25.1. About the Interlacer IP x
25.1.1. Interlacer IP Performance and Resources
25.3. Interlacer IP Functional Description x
25.3.1. Interlacer IP Interfaces
26. Mixer Intel® FPGA IP x
26.1. About the Mixer IP 26.2. Mixer IP Parameters 26.3. Mixer IP Functional Description 26.4. Mixer IP Registers 26.5. Mixer IP Software API
26.1. About the Mixer IP x
26.1.1. Mixer IP Performance and Resources
26.3. Mixer IP Functional Description x
26.3.1. Mixer IP Interfaces
27. Pixels in Parallel Converter Intel® FPGA IP x
27.1. About the Pixels in Parallel Converter IP 27.2. Pixels in Parallel IP Converter Parameters 27.3. Pixels in Parallel Converter Interfaces 27.4. Pixels in Parallel Converter Registers 27.5. Pixels in Parallel Converter IP Software API
27.1. About the Pixels in Parallel Converter IP x
27.1.1. Pixels in Parallel IP Converter Performance and Resources
28. Scaler Intel® FPGA IP x
28.1. About the Scaler 28.2. Scaler IP Parameters 28.3. Scaler IP Functional Description 28.4. Scaler IP Registers 28.5. Scaler IP Software API
28.1. About the Scaler x
28.1.1. Scaler IP Performance and Resources
28.2. Scaler IP Parameters x
28.2.1. Scaler Maximum Resolution
28.3. Scaler IP Functional Description x
28.3.1. Coefficient Selection 28.3.2. Coefficient Quantization 28.3.3. Partial Frame Scaling 28.3.4. 422 and 420 Chroma Sampled Data Scaling 28.3.5. Scaler IP Interfaces
28.3.1. Coefficient Selection x
28.3.1.1. Updating Scaler IP Runtime Coefficients
29. Stream Cleaner Intel® FPGA IP x
29.1. About the Stream Cleaner IP 29.2. Stream Cleaner IP Parameters 29.3. Stream Cleaner IP Functional Description
29.1. About the Stream Cleaner IP x
29.1.1. Stream Cleaner IP Performance and Resources
29.3. Stream Cleaner IP Functional Description x
29.3.1. Stream Cleaner IP Interfaces
30. Switch Intel® FPGA IP x
30.1. About the Switch IP 30.2. Switch IP Parameters 30.3. Switch IP Functional Description 30.4. Switch IP Registers 30.5. Switch IP Software API
30.1. About the Switch IP x
30.1.1. Switch IP Performance and Resources
30.3. Switch IP Functional Description x
30.3.1. Switch IP Latency 30.3.2. Switch IP Interfaces
31. Tone Mapping Operator Intel® FPGA IP x
31.1. About the Tone Mapping Operator IP 31.2. TMO IP Parameters 31.3. TMO IP Block Description 31.4. TMO IP Registers 31.5. TMO IP Software API
31.1. About the Tone Mapping Operator IP x
31.1.1. TMO IP Features 31.1.2. TMO IP Performance and Resource Utilization
31.3. TMO IP Block Description x
31.3.1. TMO IP Interfaces 31.3.2. TMO IP Latency
32. Test Pattern Generator Intel® FPGA IP x
32.1. About the Test Pattern Generator IP 32.2. Test Pattern Generator IP Parameters 32.3. Test Pattern Generator IP Functional Description 32.4. Test Pattern Generator IP Registers 32.5. Test Pattern Generator IP Software API
32.1. About the Test Pattern Generator IP x
32.1.1. Test Pattern Generator IP Performance and Resources
32.3. Test Pattern Generator IP Functional Description x
32.3.1. Test Pattern Generator IP Interfaces
33. Video Frame Buffer Intel® FPGA IP x
33.1. About the Video Frame Buffer IP 33.2. Video Frame Buffer IP Parameters 33.3. Video Frame Buffer IP Functional Description 33.4. Video Frame Buffer IP Registers 33.5. Video Frame Buffer IP Software API
33.1. About the Video Frame Buffer IP x
33.1.1. Video Frame Buffer Performance and Resources
33.3. Video Frame Buffer IP Functional Description x
33.3.1. Video Frame Buffer IP Interfaces
34. Video Streaming FIFO Intel® FPGA IP x
34.1. About the Video Streaming FIFO IP 34.2. Video Streaming FIFO IP Parameters 34.3. Video Streaming FIFO IP Interfaces
34.1. About the Video Streaming FIFO IP x
34.1.1. Video Streaming FIFO IP Performance and Resources
35. Video Timing Generator Intel® FPGA IP x
35.1. About the Video Timing Generator IP 35.2. Video Timing Generator IP Parameters 35.3. Video Timing Generator IP Functional Description 35.4. Video Timing Generator IP Interfaces 35.5. Video Timing Generator IP Registers 35.6. Video Timing Generator IP Software API
35.1. About the Video Timing Generator IP x
35.1.1. Video Timing Generator IP Features 35.1.2. Video Timing Generator IP Performance and Resources
36. Warp Intel® FPGA IP x
36.1. About the Warp IP 36.2. Warp IP Parameters 36.3. Warp IP Block Description 36.4. Warp IP Registers 36.5. Warp IP Software API
36.1. About the Warp IP x
36.1.1. Warp IP Features 36.1.2. Warp IP Performance and Resource Utilization
36.3. Warp IP Block Description x
36.3.1. Block Cache Tool 36.3.2. Warp IP Interfaces 36.3.3. Warp IP Latency 36.3.4. External Memory for Warp IP
36.5. Warp IP Software API x
36.5.1. Using Warp IP Software 36.5.2. Warp IP Software Code Examples
37. Design Security x
37.1. Memory Subsystems 37.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Generic Crosspoint Intel® FPGA IP
23. Genlock Signal Router Intel® FPGA IP
24. Guard Bands Intel® FPGA IP
25. Interlacer Intel® FPGA IP
26. Mixer Intel® FPGA IP
27. Pixels in Parallel Converter Intel® FPGA IP
28. Scaler Intel® FPGA IP
29. Stream Cleaner Intel® FPGA IP
30. Switch Intel® FPGA IP
31. Tone Mapping Operator Intel® FPGA IP
32. Test Pattern Generator Intel® FPGA IP
33. Video Frame Buffer Intel® FPGA IP
34. Video Streaming FIFO Intel® FPGA IP
35. Video Timing Generator Intel® FPGA IP
36. Warp Intel® FPGA IP
37. Design Security
38. Document Revision History for Video and Vision Processing Suite User Guide

10.6. Chroma Key IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_chroma_key_regs.h

Include file: intel_vvp_chroma_key.h

Table 93.  Chroma Key IP Software API
Name Description
intel_vvp_chroma_key_init Initialize the Chroma Key instance
intel_vvp_core_* Accessors defined in Video and Vision Processing IPs Software Programming Model . Writable when Lite mode is on. Readable when Lite mode is off and Debug features is on.
intel_vvp_chroma_key_get_lite_mode Returns if Lite mode is on
intel_vvp_chroma_key_get_debug_enabled Returns if Debug features is on
intel_vvp_chroma_key_get_constant_alpha_mode Returns if Constant alpha mode is on
intel_vvp_chroma_key_get_constant_alpha_value Returns the constant alpha value if Constant alpha mode is on
intel_vvp_chroma_key_get_bits_per_sample Returns the bits per color sample value
intel_vvp_chroma_key_get_num_planes Returns the number of color planes
intel_vvp_chroma_key_is_running Returns if the IP is currently processing video data
intel_vvp_chroma_key_get_commit_status Returns if IP has uncommitted writes
intel_vvp_chroma_key_get_status Reads the status register
intel_vvp_chroma_key_set_matched_alpha Sets the alpha value for matched pixels
intel_vvp_chroma_key_set_unmatched_alpha Sets the alpha value for unmatched pixels
intel_vvp_chroma_key_enable_c1_matching Enables the first color plane when checking for matches
intel_vvp_chroma_key_disable_c1_matching Disables the first color plane when checking for matches
intel_vvp_chroma_key_enable_c2_matching Enables the second color plane when checking for matches
intel_vvp_chroma_key_disable_c2_matching Disables the second color plane when checking for matches
intel_vvp_chroma_key_enable_c3_matching Enables the third color plane when checking for matches
intel_vvp_chroma_key_disable_c3_matching Disables the third color plane when checking for matches
intel_vvp_chroma_key_enable_c1_replacement Enables the swapping of the first color plane sample in case of a match
intel_vvp_chroma_key_disable_c1_replacement Disables the swapping of the first color plane sample in case of a match
intel_vvp_chroma_key_enable_c2_replacement Enables the swapping of the second color plane sample in case of a match
intel_vvp_chroma_key_disable_c2_replacement Disables the swapping of the second color plane sample in case of a match
intel_vvp_chroma_key_enable_c3_replacement Enables the swapping of the third color plane sample in case of a match
intel_vvp_chroma_key_disable_c3_replacement Disables the swapping of the third color plane sample in case of a match
intel_vvp_chroma_key_commit_writes Commit all outstanding writes

intel_vvp_chroma_key_init

Prototype 
int intel_vvp_chroma_key_init(intel_vvp_chroma_key_instance *instance, intel_vvp_core_base base);
Description

Initializes an Chroma Key instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance is not fully initialized and the application should not use it further if returning a non-zero error code.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

base - base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the Chroma Key product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpChroma KeyRegMapVersionErr if the register map is not supported

intel_vvp_chroma_key_get_lite_mode

Prototype 
bool intel_vvp_chroma_key_get_lite_mode(intel_vvp_chroma_key_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_chroma_key_get_debug_enabled

Prototype 
 bool intel_vvp_chroma_key_get_debug_enabled(intel_vvp_chroma_key_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_chroma_key_get_constant_alpha_mode

Prototype 
 bool intel_vvp_chroma_key_get_constant_alpha_mode(intel_vvp_chroma_key_instance *instance);
Description

Returns the value of the CONSTANT_ALPHA_MODE register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

true if the IP is parameterized to add a constant alpha value to the video stream

intel_vvp_chroma_key_get_constant_alpha_value

Prototype 
 uint16_t intel_vvp_chroma_key_get_constant_alpha_value(intel_vvp_chroma_key_instance *instance);
Description

Returns the value of the CONSTANT_ALPHA_VALUE register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized and parameterized for constant alpha mode

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

The constant alpha value if the IP is parameterized with constant alpha mode

intel_vvp_chroma_key_get_bits_per_sample

Prototype 
 uint8_t intel_vvp_chroma_key_get_bits_per_sample(intel_vvp_chroma_key_instance *instance);
Description

Returns the value of the BITS_PER_SAMPLES parameter used to configure the IP. The instance must be a valid intel_vvp_chroma_key_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

the number of bits per color sample

intel_vvp_chroma_key_get_num_planes

Prototype 
 uint8_t intel_vvp_chroma_key_get_num_planes(intel_vvp_chroma_key_instance *instance);
Description

Returns the value of the NUMBER_OF_COLOR_PLANES parameter used to configure the IP. The instance must be a valid intel_vvp_chroma_key_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

the number of color planes per pixel

intel_vvp_chroma_key_is_running

Prototype 
 bool intel_vvp_chroma_key_is_running(intel_vvp_chroma_key_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

True is the IP is currently receiving/storing an input field, false when between two input fields

intel_vvp_chroma_key_get_commit_status

Prototype 
 bool intel_vvp_chroma_key_get_commit_status(intel_vvp_clipper_instance* instance);
Description

Reads and returns the commit pending bit of the STATUS register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized and configured in full mode.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

True is the IP is configured in full mode and if the agent interface contains uncommitted writes.

intel_vvp_chroma_key_get_status

Prototype 
 uint32_t intel_vvp_chroma_key_get_status(intel_vvp_chroma_key_instance* instance);
Description

Reads the STATUS register. The instance must be a valid intel_vvp_chroma_key_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

The content of the STATUS register

intel_vvp_chroma_key_set_matched_alpha

Prototype 
 int intel_vvp_chroma_key_set_matched_alpha(intel_vvp_chroma_key_instance *instance, uint16_t matched_alpha);
Description

Sets the alpha value for matched pixels. The instance must be a valid intel_vvp_chroma_key_instance fully initialized and not parameterized for constant alpha mode.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

matched_alpha - the alpha value for matched pixels in the range [0..bits_per_sample-1]

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha only

kIntelVvpChromaKeyValueErr if the matched alpha is invalid

intel_vvp_chroma_key_set_unmatched_alpha

Prototype 
 int intel_vvp_chroma_key_set_unmatched_alpha(intel_vvp_chroma_key_instance *instance, uint16_t unmatched_alpha);
Description

Sets the alpha value for unmatched pixels. The instance must be a valid intel_vvp_chroma_key_instance fully initialized and not parameterized for constant alpha mode.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

unmatched_alpha - the alpha value for unmatched pixels in the range [0..bits_per_sample-1]

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

kIntelVvpChromaKeyValueErr if the unmatched alpha is invalid

intel_vvp_chroma_key_enable_c1_matching

Prototype 
 int intel_vvp_chroma_key_enable_c1_matching(intel_vvp_chroma_key_instance *instance, uint16_t c1_lower_bound, uint16_t c1_upper_bound);
Description

Enables pixel matching with the first color sample value

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

c1_lower_bound - the lowest sample value, in the range [0..bits_per_sample-1], to match a color sample

c1_upper_bound - the highest sample value, in the range [0..bits_per_sample-1], to match a color sample

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output

kIntelVvpChromaKeyValueErr if the lower bound or upper bound are invalid

intel_vvp_chroma_key_disable_c1_matching

Prototype 
 int intel_vvp_chroma_key_disable_c1_matching(intel_vvp_chroma_key_instance* instance);
Description

Disables pixel matching with the first color sample value

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output

intel_vvp_chroma_key_enable_c2_matching

Prototype 
 int intel_vvp_chroma_key_enable_c1_matching(intel_vvp_chroma_key_instance *instance, uint16_t c2_lower_bound, uint16_t c2_upper_bound);
Description

Enables pixel matching with the second color sample value

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

c2_lower_bound - the lowest sample value, in the range [0..bits_per_sample-1], to match a color sample

c2_upper_bound - the highest sample value, in the range [0..bits_per_sample-1], to match a color sample

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than two color planes

kIntelVvpChromaKeyValueErr if the lower bound or upper bound are invalid

intel_vvp_chroma_key_disable_c2_matching

Prototype 
 int intel_vvp_chroma_key_disable_c2_matching(intel_vvp_chroma_key_instance* instance);
Description

Disables pixel matching with the second color sample value

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than two color planes

intel_vvp_chroma_key_enable_c3_matching

Prototype 
 int intel_vvp_chroma_key_enable_c3_matching(intel_vvp_chroma_key_instance *instance, uint16_t c3_lower_bound, uint16_t c3_upper_bound);
Description

Enables pixel matching with the third color sample value

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

c3_lower_bound - the lowest sample value, in the range [0..bits_per_sample-1], to match a color sample

c3_upper_bound - the highest sample value, in the range [0..bits_per_sample-1], to match a color sample

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than three color planes

kIntelVvpChromaKeyValueErr if the lower bound or upper bound are invalid

intel_vvp_chroma_key_disable_c3_matching

Prototype 
 int intel_vvp_chroma_key_disable_c3_matching(intel_vvp_chroma_key_instance* instance);
Description

Disables pixel matching with the third color sample value

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than three color planes

intel_vvp_chroma_key_enable_c1_replacement

Prototype 
 int intel_vvp_chroma_key_enable_c1_replacement(intel_vvp_chroma_key_instance *instance, uint16_t c1_replacement)
Description

Swaps the first color plane sample value when a pixel is matched

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

c1_replacement - the replacement sample value, in the range [0..bits_per_sample-1], when a pixel was matched

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output

kIntelVvpChromaKeyValueErr if the replacement value is invalid

intel_vvp_chroma_key_disable_c1_replacement

Prototype 
int intel_vvp_chroma_key_disable_c1_replacement(intel_vvp_chroma_key_instance *instance)
Description

Cancels the swap of the first color plane sample value when a pixel is matched

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output

intel_vvp_chroma_key_enable_c2_replacement

Prototype 
 int intel_vvp_chroma_key_enable_c2_replacement(intel_vvp_chroma_key_instance *instance, uint16_t c2_replacement)
Description

Swaps the second color plane sample value when a pixel is matched

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

c2_replacement - the replacement sample value, in the range [0..bits_per_sample-1], when a pixel was matched

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than two color planes

kIntelVvpChromaKeyValueErr if the replacement value is invalid

intel_vvp_chroma_key_disable_c2_replacement

Prototype 
int intel_vvp_chroma_key_disable_c2_replacement(intel_vvp_chroma_key_instance *instance)
Description

Cancels the swap of the second color plane sample value when a pixel is matched

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than two color planes

intel_vvp_chroma_key_enable_c3_replacement

Prototype 
 int intel_vvp_chroma_key_enable_c3_replacement(intel_vvp_chroma_key_instance *instance, uint16_t c3_replacement)
Description

Swaps the third color plane sample value when a pixel is matched

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

c3_replacement - the replacement sample value, in the range [0..bits_per_sample-1], when a pixel was matched

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than three color planes

kIntelVvpChromaKeyValueErr if the replacement value is invalid

intel_vvp_chroma_key_disable_c3_replacement

Prototype 
int intel_vvp_chroma_key_disable_c3_replacement(intel_vvp_chroma_key_instance *instance)
Description

Cancels the swap of the third color plane sample value when a pixel is matched

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid or parameterized for constant alpha output or with less than three color planes

intel_vvp_chroma_key_commit_writes

Prototype 
 int intel_vvp_chroma_key_commit_writes(intel_vvp_chroma_key_instance* instance)
Description

Commits all pending writes before processing the next field. The instance must be valid and parameterized in full mode.

Arguments

instance - pointer to the intel_vvp_chroma_key_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

Related Information
Level Two Title