Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

10.2. Chroma Key IP Parameters

The IP offers compile-time parameters.
Table 58.  Chroma Key IP Parameters
Parameter Values Description
Video Data Format
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
Number of color planes 1 or 3 Select the number of input color planes per pixel. (Output color planes are N+1 for carriage of alpha channel)
Bits per color sample 8 to 16 Select the number of bits per color sample.
Lite mode On or off Turn on to use the lite variant of the Intel FPGA Streaming Video protocol.
Memory-mapped control interface On or off

Turn on to specify the pixel matching ranges and alpha values for pixel tagging.

The memory-mapped control interface is mandatory in lite mode.

Separate clock for control interface On or off Turn on to enable a separate clock for the control interface.
Chroma Key Behavior
Constant Alpha Mode On or off Turn on for constant alpha mode.
Constant Alpha Tag 0 to 65535 If Constant Alpha Mode is on, the IP appends the Constant Alpha Tag value to each pixel.
Debug features On or off Turn on for debug features (not applicable for lite mode).
Pipeline Ready On or off Turn on to pipeline the Tready signal.
Figure 18. Chroma Key IP GUI