Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 12/06/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Transceiver Power Supply Operating Conditions

Table 8.  E-Tile Transceiver Power Supply Operating Conditions for Intel® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol Description Typical DC Level (V) Recommended DC Setpoint (% of Vnominal) Recommended VR Ripple (% of Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) Unit
VCCRT_GXE 15 Transceiver power supply 0.9 ± 0.5% ± 2.5% ± 3% V
VCC_HSSI_GXE E-tile digital signal power supply 0.9 ± 0.5% ± 2.5% ± 3% V
VCCRTPLL_GXE 15 Transceiver PLL power supply 0.9 ± 0.5% ± 2.5% ± 3% V
VCCH_GXE Analog power supply 1.1 ± 0.5% ± 0.5% ± 2% ± 3% V
VCCCLK_GXE LVPECL REFCLK power supply 2.5 ± 0.5% ± 0.5% ± 3.5% ± 5% V
Table 9.  P-Tile Transceiver Power Supply Operating Conditions for Intel® Agilex™ Devices

The specifications below should be met at the board vias directly connected to the package power balls. Place the VR sense point in the FPGA pinfield (in the package shadow), as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.

For specification status, see the Data Sheet Status table

Symbol Description Typical DC Level (V) Recommended DC Setpoint (% of Vnominal) Recommended VR Ripple (% of Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) Unit
VCCRT_GXP Transceiver power supply 0.9 ± 0.5% ± 2.5% ± 3% V
VCC_HSSI_GXP P-tile digital signal power supply 0.9 ± 0.5% ± 2.5% ± 3% V
VCCFUSE_GXP P-tile efuse power supply 0.9 ± 0.5% ± 2.5% ± 3% V
VCCCLK_GXP 16 P-tile I/O buffer power supply 1.8 ± 0.5% ± 0.5% ± 2% ± 3% V
VCCH_GXP 16 High voltage power for transceiver 1.8 ± 0.5% ± 0.5% ± 2% ± 3% V
Table 10.  R-Tile Transceiver Power Supply Operating Conditions for Intel® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol Description Typical DC Level (V) Recommended DC Setpoint (% of Vnominal) Recommended VR Ripple (% of Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) Unit
VCCH_GXR[L,R] 17 Transceiver analog high voltage power 1.8 ±0.8% ±2% ±2.8% V
VCCRT_GXR[L,R] Transceiver analog power supply 1 ±0.5% ±2.5% ±3% V
VCCED_GXR[L,R] Transceiver digital power supply 0.9 ±0.8% ±2.5% ±3.3% V
VCCE_PLL_GXR[L,R] PLLs power supply 1 ±0.5% ±1.5% ±2% V
VCCE_DTS_GXR[L,R] DTS power supply 1 ±0.5% ±1.5% ±2% V
VCCCLK_GXR[L,R] 17 Reference clock power supply 1 ±0.5% ±2.5% ±3% V
VCCHFUSE_GXR R-tile efuse power supply 1 ±0.5% ±2.5% ±3% V
VCC_HSSI_GXR Digital signal power supply 0.9 ±0.8% ±2.5% ±3.3% V
Table 11.  F-Tile Transceiver Power Supply Operating Conditions for Intel® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol Description Typical DC Level (V) Recommended DC Setpoint (% of Vnominal) Recommended VR Ripple (% of Vnominal) Recommended AC Transient (% of Vnominal) Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal) Unit
VCC_HSSI_GXF F-tile digital signal power supply 0.8 ±0.5% ±0.5% ±2.5% ±3% V
VCCFUSECORE_GXF F-tile fuse writing power supply 1 ±0.5% ±4.5% ±5% V
VCCFUSEWR_GXF F-tile efuse power supply 1 ±0.5% ±4.5% ±5% V
VCCCLK_GXF Reference clock power supply 1.8 ±0.5% ±0.5% ±2% ±3% V
VCCERT1_FHT_GXF 18 FHT analog core supply 1 1 ±0.5% ±0.5% ±1.5% ±2.5% V
VCCERT2_FHT_GXF 19 FHT analog core supply 2 1 ±0.5% ±0.5% ±1.5% ±2.5% V
VCCEHT_FHT_GXF 20 FHT high voltage power supply for analog circuit 1.5 ±0.5% ±0.5% +1%/–1.5% +2%/–2.5% V
VCCERT_FGT_GXF 21 FGT analog core supply alone 1 ±0.5% ±0.5% ±1.5% ±3% V
FGT analog core supply when combined with VCCERT1_FHT_GX and VCCERT2_FHT_GXF 1 V supply 1 ±0.5% ±0.5% ±1.5% ±2.5% V
VCCH_FGT_GXF 21 FGT analog I/O power supply 1.8 ±0.5% ≤5 mV ±1.5% ±3% V
Related Information
15 The difference between VCCRT/VCCRTPLL and VCCH should be no less than 200 mV.
16 Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies.
17 Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies.
18 HF noise requires AC 10 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤5 mVpp.
19 HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤5 mVpp.
20 HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤7 mVpp.
21 HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple: ≤5mVpp.
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