L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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Document Table of Contents

3. Interface Overview

The PCI Express Base Specification 3.0 defines a packet interface for communication between a Root Port and an Endpoint. When you select the Avalon® -ST interface, Transaction Layer Packets (TLP) transfer data between the Root Port and an Endpoint using the Avalon-ST TX and RX interfaces. The interfaces are named from the point-of-view of the user logic.

Figure 17.  Intel® Stratix® 10 Top-Level Interfaces

The following figures show the PCIe hard IP Core top-level interfaces and the connections to the Application Layer and system.

Figure 18. Connections: User Application to Intel L-/H-tile Avalon-ST IP for PCI Express IP Core
Figure 19. Connections: PCIe Link and Reconfiguration, Power and Test Interfaces

The following sections introduce these interfaces. Refer to the Interfaces section in the Block Description chapter for detailed descriptions and timing diagrams.