L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public
Document Table of Contents

2.6. Compiling the Design Example and Programming the Device

  1. Navigate to <project_dir>/pcie_s10_hip_avmm_bridge_0_example_design/ and open pcie_example_design.qpf.
  2. On the Processing menu, select Start Compilation.
  3. After successfully compiling your design, program the targeted device with the Programmer.

Did you find the information on this page useful?

Characters remaining:

Feedback Message