L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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Document Table of Contents

6.1.13. Control Shadow Interface for SR-IOV

The control shadow interface provides access to the current settings for some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces located in the SR-IOV Bridge. This interface is only available for H-Tile devices.

Use this interface for the following purposes:

  • To monitor specific VF registers using the ctl_shdw_update output and the associated output signals defined below.
  • To monitor all VF registers using the the ctl_shdw_req_all input to request a full scan of the register fields for all active VFs.




ctl_shdw_update Output The SR-IOV Bridge asserts this output for 1 clock cycle when one or more of the register fields being monitored is updated. The ctl_shdw_cfg outputs drive the new values. ctl_shdw_pf_num, ctl_shdw_vf_num, and ctl_shdw_vf_active identify the VF and its PF.
Note: When ctl_shdw_update is asserted, the ctl_shdw_* outputs are valid.


Output Identifies the PF whose register settings are on the ctl_shdw_cfg outputs. When the function is a VF, this input specifies the PF number to which the VF is attached.
ctl_shdw _vf_active Output When asserted, indicates that the function whose register settings are on the ctl_shdw_cfg outputs is a VF. ctl_shdw_vf_num drives the VF number offset.
ctl_shdw_vf_num[10:0] Output Identifies the VF number offset of the VF whose register settings are on ctl_shdw_cfg outputs when ctl_shdw _vf_active is asserted, Its value ranges from 0-(<n>-1) , where <n> is the number of VFs attached to the associated PF.
ctl_shdw_cfg[6:0] Output

When ctl_shdw_update is asserted, this output provides the current settings of the register fields of the associated function. The bits specify the following register fields:

  • [0]: Bus Master Enable, bit[2] of the PCI Command Register.
  • [1]: MSI-X function mask field, bit[14] of the MSI-X Message Control register
  • [2]: MSI-X enable field, bit[15] of the MSI-X Message Control register
  • [4:3]: TPH Steering Tag (ST) Mode Select field, bits[1:0] of the TPH Requester Control register
  • [5]: TPH Requester Enable field, bit[8] of the TPH Requester Control register
  • [6]: Enable field, bit[15] of the ATS Control register
ctl_shdw_req_all Input

When asserted, requests a complete scan of the register fields being monitored for all active Functions. When the ctl_shdw_req_all input is asserted, the SR-IOV bridge cycles through each VF. It provides the current values of all register fields. If a Configuration Write occurs during a scan, the SR-IOV Bridge interrupts the scan to output the new setting. It then resumes the scan, continuing sequentially from the updated VF setting.

The SR-IOV Bridge checks the state of ctl_shdw_req_all at the end of each scan cycle. It starts a new scan cycle if this input is asserted.

Connect this input to logic 1 to scan the functions continuously.