L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public
Document Table of Contents

3.1. Avalon-ST RX Interface

The Transaction Layer transfers TLPs to the Application on this interface. The Application must assert rx_st_ready before transfers can begin.

This interface is not strictly Avalon® -ST compliant, and does not have a well-defined ready_latency. For all variants other than the Gen3 x16 variant, the latency between the assertion or de-assertion of rx_st_ready and the corresponding de-assertion or assertion of rx_st_valid can be up to 17 cycles. Once rx_st_ready deasserts, rx_st_valid deasserts within 17 cycles. Once rx_st_ready reasserts, rx_st_valid resumes data transfer within 17 cycles. To achieve the best performance the Application must include a receive buffer large enough to avoid the deassertion of rx_st_ready. Refer to Avalon-ST RX Interface for more information.

For the Gen3 x16 variant, once rx_st_ready deasserts, rx_st_valid deasserts within 18 cycles. Once rx_st_ready reasserts, rx_st_valid resumes data transfer within 18 cycles.

Note: Throughout this user guide the terms Application and Application Layer refer to your logic that interfaces with the PCIe Transaction Layer.

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