L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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Document Table of Contents

6.2. Errors reported by the Application Layer

The Application Layer uses the app_err_* interface to report errors to the IP core.

The Application Layer reports the following types of errors to the IP core:

  • Unexpected Completion
  • Completer Abort
  • CPL Timeout
    Note: The IP core does not contain the completion timeout checking logic. You need to implement this functionality in your application logic.
  • Unsupported Request
  • Poisoned TLP received
  • Uncorrected Internal Error, including ECC and parity errors flagged by the core
  • Corrected Internal Error, including Corrected ECC errors flagged by the core
  • Advisory NonFatal Error

For Advanced Error Reporting (AER), the Application Layer provide the information to log the TLP header and the error log request via the app_err_* interface.

The Application Layer completes the following steps to report an error to the IP core:

  • Sets the corresponding status bits in the PCI Status register, and the PCIe Device Status register
  • Sets the appropriate status bits and header log in the AER registers if AER is enabled
  • Indicates the Error event to the upstream component:
    • Endpoints transmit an Message upstream
    • Root Ports assert app_serr_out to the Application Layer if an error is detected or if an error Message is received from a downstream component. The Root Port also forwards the error Message from the downstream component on the Avalon® -ST RX interface. The Application Layer may choose to ignore this information. (Root Ports are not supported in the Quartus® Prime Pro – Stratix 10 Edition 17.1 Interim Release.)