L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.10.12. Address Translation Services ATS Enhanced Capability Header

Table 85.  Address Translation Services ATS Enhanced Capability Header Register - 0x284

Bits

Register Description

Default Value

Access

[31:20]

Next Capability Pointer: Points to NULL.

0

RO

[19:16] Capability Version. 1

RO

[15:0] PCI Express Extended Capability ID 0x003C

RO