L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
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8.1.10.3. Initial VFs and Total VFs Registers

Table 72.  Initial VFs and Total VFs Registers - 0x1C4

Bits

Description

Default Value

Access

[15:0]

Initial VFs. Specifies the initial number of VFs configured for this PF.

Same value as TotalVFs

RO

[31:16]

Total VFs. Specifies the total number of VFs attached to this PF.

Set in Platform Designer

RO
Table 73.  Function Dependency Link and NumVFs Registers - 0x1C8

Bit Location

Description

Default Value

Access

[15:0]

NumVFs. Specifies the number of VFs enabled for this PF. Writable only when the VF Enable bit in the SR-IOV Control Register is 0.

0

RW

[31:16]

Function Dependency Link

0

RO

Table 74.  VF Offset and Stride Registers - 0x1CC

Bits

Register Description

Default Value

Access

[31:16]

VF Stride

1

RO