L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Document Table of Contents

3.5. Clocks

The PCI Express Card Electromechanical Specification Revision 2.0 defines the input reference clock. It is a 100 MHz ±300 ppm. The motherboard drives this clock to the PCIe card. The PCIe card is not required to use the reference clock received from the connector. However, the PCIe card must provide a 100 MHz ±300 ppm to the refclk input pin. This input reference clock must be stable and free-running at device power-up for a successful configuration of the device.
Table 9.  Application Clock Frequency
Data Rate Interface Width coreclkout_hip Frequency
Gen1 x1, x2, x4, x8, and x16 256 bits 125 MHz
Gen2 x1, x2, x4, and x8 256 bits 125 MHz
Gen2 x16 256 bits 250 MHz
Gen3 x1, x2, and x4 256 bits 125 MHz
Gen3 x8 256 bits 250 MHz
Gen3 x16 512 bits 250 MHz

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