L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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6.1.4. Avalon-ST 256-Bit TX Interface

The Application Layer transfers data to the Transaction Layer of the PCIe IP core over the Avalon-ST TX interface. This is a 256-bit interface.
Table 33.  256‑Bit Avalon-ST TX Datapath






Data for transmission. The Application Layer must provide a properly formatted TLP on the TX interface. Valid when tx_st_valid is asserted (subject to the ready latency, see below). The mapping of message TLPs is the same as the mapping of Transaction Layer TLPs with 4 dword headers. The number of data cycles must be correct for the length and address fields in the header. Issuing a packet with an incorrect number of data cycles results in the TX interface hanging and becoming unable to accept further requests. In addition, the TLP must be no larger than the negotiated Max Payload size.

For the TLP requester ID field, bits[31:16] in dword1 specify the following information:

  • Bits[19:16]: Specify the PF number.
  • Bits[31:20]: Specify the VF number. The VF number is valid when tx_st_vf_active is asserted. If the request is from VF[<m>,<n>], then bits[19:16] drive the PF number, <m>, and bits [31:20] drive the VF number, <n>. The tx_st_vf_active signal asserts in the same cycle as tx_st_sop and tx_st_valid.

Refer to the TLP Header and Data Alignment for the Avalon-ST TX and Avalon-ST RX Interfaces for the layout of TLP headers and data.



Indicates first cycle of a TLP when asserted together with tx_st_valid.



Indicates last cycle of a TLP when asserted together with tx_st_valid.



Indicates that the Transaction Layer is ready to accept data for transmission. The core deasserts this signal to throttle the data stream. tx_st_ready may be asserted during reset. The Application Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon-ST TX interface. The reset_status signal can also be used to monitor when the IP core has come out of reset.

If tx_st_ready is asserted by the Transaction Layer on cycle <n>, then <n> + readyLatency is a ready cycle, during which the Application Layer may assert tx_st_valid and transfer data.

If tx_st_ready is deasserted by the Transaction Layer on cycle <n>, then the Application Layer must deassert tx_st_valid within the readyLatency number of cycles after cycle <n>.

The readyLatency is 3 coreclkout_hip cycles.

This interface is not strictly Avalon® -ST compliant.



Clocks tx_st_data to the core when tx_st_ready is also asserted. Between tx_st_sop and the corresponding tx_st_eop, tx_st_valid must not be deasserted, except in response to tx_st_ready deassertion. When tx_st_ready deasserts in the middle of a packet, this signal must deassert exactly 3 coreclkout_hip cycles later. When tx_st_ready reasserts, and tx_st_data is in mid-TLP, this signal must reassert within 3 cycles. The figure entitled Avalon-ST TX Interface tx_st_ready Deasserts illustrates the timing of this signal.

To facilitate timing closure, Intel recommends that you register both the tx_st_ready and tx_st_valid signals.



Forces an error on transmitted TLP. This signal is used to nullify a packet. To nullify a packet, assert this signal for 1 cycle with tx_st_eop. When a packet is nullified, the following packet should not be transmitted until the next clock cycle.

Note: You cannot nullify a packet with 8 DW or less of data.


The IP core supports byte parity. Each bit represents even parity of the associated byte of the tx_st_data bus. For example, bit[0] corresponds to tx_st_data[7:0], bit[1] corresponds to tx_st_data[15:8], and so on.

tx_st_vf_active H-Tile Input

When asserted, the transmitting TLP is for a VF. When deasserted, the transmitting TLP is for a PF. Valid when tx_st_sop is asserted.

Valid when multiple virtual functions are enabled.