L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
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4.9. Example Designs

Table 26.  Example Designs

Parameter

Value

Description

Available Example Designs

PIO

The DMA example design uses the Write Data Mover, Read Data Mover, and a custom Descriptor Controller.

When you select the PIO option, the generated design includes a target application including only downstream transactions.

The PIO design example is the only option for the Avalon® -ST interface.

Simulation On/Off When On, the generated output includes a simulation model.
Synthesis On/Off When On, the generated output includes a synthesis model.
Generated HDL format

Verilog/VHDL

Only Verilog HDL is available in the current release.

Target Development Kit

None

Intel® Stratix® 10 H-Tile ES1 Development Kit

Intel® Stratix® 10 L-Tile ES2 Development Kit

Select the appropriate development board.

If you select one of the development boards, system generation overwrites the device you selected with the device on that development board.
Note: If you select None, system generation does not make any pin assignments. You must make the assignments in the .qsf file.