L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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6.5.2. Configuration Retry Status

The Intel L-/H-Tile Avalon-ST for PCI Express IP is part of the periphery image of the device. After power-up, the periphery image is loaded first. The End Point can then respond to Configuration Requests with Config Retry Status (CRS) to delay the enumeration process until after the FPGA fabric is configured.