Visible to Intel only — GUID: vwf1504108927660
Ixiasoft
Visible to Intel only — GUID: vwf1504108927660
Ixiasoft
3.2. Avalon-ST TX Interface
The Application transmits TLPs to the Transaction Layer of the IP core on this interface. The Transaction Layer must assert tx_st_ready before transmission begins. Transmission of a packet must be uninterrupted when tx_st_ready is asserted. The readyLatency of this interface is three coreclkout_hip cycles. For more detailed information about the Avalon-ST interface, refer to Avalon-ST TX Interface. The packet layout is shown in detail in the Block Description chapter.
Did you find the information on this page useful?
Feedback Message
Characters remaining: