L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

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ID 683111
Date 3/07/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Interrupts 8. Registers 9. Testbench and Design Example 10. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. TX Credit Adjustment Sample Code C. Root Port Enumeration D. Document Revision History
1. Introduction x
1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Recommended Fabric Speed Grades 1.6. Performance and Resource Utilization 1.7. Transceiver Tiles 1.8. PCI Express IP Core Package Layout 1.9. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
3. Interface Overview x
3.1. Avalon-ST RX Interface 3.2. Avalon-ST TX Interface 3.3. TX Credit Interface 3.4. TX and RX Serial Data 3.5. Clocks 3.6. Function-Level Reset (FLR) Interface 3.7. Control Shadow Interface for SR-IOV 3.8. Configuration Extension Bus Interface 3.9. Hard IP Reconfiguration Interface 3.10. Interrupt Interfaces 3.11. Power Management Interface 3.12. Reset 3.13. Transaction Layer Configuration Interface 3.14. PLL Reconfiguration Interface 3.15. PIPE Interface (Simulation Only)
4. Parameters x
4.1. Stratix 10 Avalon-ST Settings 4.2. Multifunction and SR-IOV System Settings 4.3. Base Address Registers 4.4. Device Identification Registers 4.5. TPH/ATS Capabilities 4.6. PCI Express and PCI Capabilities Parameters 4.7. Configuration, Debug and Extension Options 4.8. PHY Characteristics 4.9. Example Designs
4.6. PCI Express and PCI Capabilities Parameters x
4.6.1. Device Capabilities 4.6.2. Link Capabilities 4.6.3. MSI and MSI-X Capabilities 4.6.4. Slot Capabilities 4.6.5. Power Management 4.6.6. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Integration and Implementation 5.5. Required Supporting IP Cores 5.6. Channel Layout and PLL Usage
5.2. Simulation x
5.2.1. Selecting Serial or PIPE Simulation
5.4. Integration and Implementation x
5.4.1. Clock Requirements 5.4.2. Reset Requirements
5.5. Required Supporting IP Cores x
5.5.1. Hard Reset Controller 5.5.2. TX PLL
6. Block Descriptions x
6.1. Interfaces 6.2. Errors reported by the Application Layer 6.3. Power Management 6.4. Transaction Ordering 6.5. RX Buffer
6.1. Interfaces x
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 6.1.2. Avalon-ST 256-Bit RX Interface 6.1.3. Avalon-ST 512-Bit RX Interface 6.1.4. Avalon-ST 256-Bit TX Interface 6.1.5. Avalon-ST 512-Bit TX Interface 6.1.6. TX Credit Interface 6.1.7. Interpreting the TX Credit Interface 6.1.8. Clocks 6.1.9. Update Flow Control Timer and Credit Release 6.1.10. Function-Level Reset (FLR) Interface 6.1.11. Resets 6.1.12. Interrupts 6.1.13. Control Shadow Interface for SR-IOV 6.1.14. Transaction Layer Configuration Space Interface 6.1.15. Configuration Extension Bus Interface 6.1.16. Hard IP Status Interface 6.1.17. Hard IP Reconfiguration 6.1.18. Power Management Interface 6.1.19. Serial Data Interface 6.1.20. PIPE Interface 6.1.21. Test Interface 6.1.22. PLL IP Reconfiguration 6.1.23. Message Handling
6.1.2. Avalon-ST 256-Bit RX Interface x
6.1.2.1. Avalon-ST RX Interface Three- and Four-Dword TLPs 6.1.2.2. Avalon-ST RX Interface rx_st_ready Deasserts for the 256-Bit Interface 6.1.2.3. Avalon-ST RX Interface rx_st_valid Deasserts 6.1.2.4. Avalon-ST RX Back-to-Back Transmission 6.1.2.5. Avalon-ST RX Interface Single-Cycle TLPs
6.1.3. Avalon-ST 512-Bit RX Interface x
6.1.3.1. PCIe TLP Layout Using the 512-Bit Interface
6.1.4. Avalon-ST 256-Bit TX Interface x
6.1.4.1. Avalon-ST TX Three- and Four-Dword TLPs 6.1.4.2. Avalon-ST TX Interface tx_st_ready Deassertion 6.1.4.3. Assertion and Deassertion of Avalon-ST TX Interface tx_st_valid
6.1.12. Interrupts x
6.1.12.1. MSI and Legacy Interrupts
6.1.23. Message Handling x
6.1.23.1. Endpoint Received Messages 6.1.23.2. Endpoint Transmitted Messages
6.2. Errors reported by the Application Layer x
6.2.1. Error Handling
6.3. Power Management x
6.3.1. Endpoint D3 Entry 6.3.2. End Point D3 Exit 6.3.3. Exit from D3 hot 6.3.4. Exit from D3 cold 6.3.5. Active State Power Management
6.4. Transaction Ordering x
6.4.1. TX TLP Ordering 6.4.2. RX TLP Ordering
6.5. RX Buffer x
6.5.1. Retry Buffer 6.5.2. Configuration Retry Status
7. Interrupts x
7.1. Interrupts for Endpoints
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Registers x
8.1. Configuration Space Registers
8.1. Configuration Space Registers x
8.1.1. Register Access Definitions 8.1.2. PCI Configuration Header Registers 8.1.3. PCI Express Capability Structures 8.1.4. Intel Defined VSEC Capability Header 8.1.5. General Purpose Control and Status Register 8.1.6. Uncorrectable Internal Error Status Register 8.1.7. Uncorrectable Internal Error Mask Register 8.1.8. Correctable Internal Error Status Register 8.1.9. Correctable Internal Error Mask Register 8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map
8.1.4. Intel Defined VSEC Capability Header x
8.1.4.1. Intel Defined Vendor Specific Header 8.1.4.2. Intel Marker 8.1.4.3. JTAG Silicon ID 8.1.4.4. User Configurable Device and Board ID
8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map x
8.1.10.1. ARI Enhanced Capability Header 8.1.10.2. SR-IOV Enhanced Capability Registers 8.1.10.3. Initial VFs and Total VFs Registers 8.1.10.4. VF Device ID Register 8.1.10.5. Page Size Registers 8.1.10.6. VF Base Address Registers (BARs) 0-5 8.1.10.7. Secondary PCI Express Extended Capability Header 8.1.10.8. Lane Status Registers 8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header 8.1.10.10. TPH Requester Capability Register 8.1.10.11. TPH Requester Control Register 8.1.10.12. Address Translation Services ATS Enhanced Capability Header 8.1.10.13. ATS Capability Register and ATS Control Register
9. Testbench and Design Example x
9.1. Endpoint Testbench 9.2. Test Driver Module 9.3. Root Port BFM Overview 9.4. BFM Procedures and Functions
9.1. Endpoint Testbench x
9.1.1. Endpoint Testbench for SR-IOV
9.3. Root Port BFM Overview x
9.3.1. BFM Memory Map 9.3.2. Configuration Space Bus and Device Numbering 9.3.3. Configuration of Root Port and Endpoint 9.3.4. Issuing Read and Write Transactions to the Application Layer
9.4. BFM Procedures and Functions x
9.4.1. ebfm_barwr Procedure 9.4.2. ebfm_barwr_imm Procedure 9.4.3. ebfm_barrd_wait Procedure 9.4.4. ebfm_barrd_nowt Procedure 9.4.5. ebfm_cfgwr_imm_wait Procedure 9.4.6. ebfm_cfgwr_imm_nowt Procedure 9.4.7. ebfm_cfgrd_wait Procedure 9.4.8. ebfm_cfgrd_nowt Procedure 9.4.9. BFM Configuration Procedures 9.4.10. BFM Shared Memory Access Procedures 9.4.11. BFM Log and Message Procedures 9.4.12. Verilog HDL Formatting Functions
9.4.9. BFM Configuration Procedures x
9.4.9.1. ebfm_cfg_rp_ep Procedure 9.4.9.2. ebfm_cfg_decode_bar Procedure
9.4.10. BFM Shared Memory Access Procedures x
9.4.10.1. Shared Memory Constants 9.4.10.2. shmem_write Task 9.4.10.3. shmem_read Function 9.4.10.4. shmem_display Verilog HDL Function 9.4.10.5. shmem_fill Procedure 9.4.10.6. shmem_chk_ok Function
9.4.11. BFM Log and Message Procedures x
9.4.11.1. ebfm_display Verilog HDL Function 9.4.11.2. ebfm_log_stop_sim Verilog HDL Function 9.4.11.3. ebfm_log_set_suppressed_msg_mask Task 9.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 9.4.11.5. ebfm_log_open Verilog HDL Function 9.4.11.6. ebfm_log_close Verilog HDL Function
9.4.12. Verilog HDL Formatting Functions x
9.4.12.1. himage1 9.4.12.2. himage2 9.4.12.3. himage4 9.4.12.4. himage8 9.4.12.5. himage16 9.4.12.6. dimage1 9.4.12.7. dimage2 9.4.12.8. dimage3 9.4.12.9. dimage4 9.4.12.10. dimage5 9.4.12.11. dimage6 9.4.12.12. dimage7
10. Troubleshooting and Observing the Link x
10.1. Troubleshooting 10.2. PCIe Link Inspector Overview
10.1. Troubleshooting x
10.1.1. Simulation Fails To Progress Beyond Polling.Active State 10.1.2. Hardware Bring-Up Issues 10.1.3. Link Training 10.1.4. Link Hangs in L0 State 10.1.5. Use Third-Party PCIe Analyzer
10.2. PCIe Link Inspector Overview x
10.2.1. PCIe* Link Inspector Hardware
10.2.1. PCIe* Link Inspector Hardware x
10.2.1.1. Enabling the PCIe* Link Inspector 10.2.1.2. Launching the PCIe* Link Inspector 10.2.1.3. The PCIe* Link Inspector LTSSM Monitor 10.2.1.4. Accessing the Configuration Space and Transceiver Registers 10.2.1.5. Additional Status Commands
10.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
10.2.1.3.1. LTSSM Monitor Registers 10.2.1.3.2. ltssm_save2file <file_name> 10.2.1.3.3. ltssm_file2console 10.2.1.3.4. ltssm_debug_check 10.2.1.3.5. ltssm_display <num_states> 10.2.1.3.6. ltssm_save_oldstates
10.2.1.4. Accessing the Configuration Space and Transceiver Registers x
10.2.1.4.1. PCIe* Link Inspector Commands 10.2.1.4.2. NPDME PLL and Channel Commands 10.2.1.4.3. Register Address Map
10.2.1.5. Additional Status Commands x
10.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
A. PCI Express Core Architecture x
A.1. Transaction Layer A.2. Data Link Layer A.3. Physical Layer
D. Document Revision History x
D.1. Document Revision History for the Intel® L- and H-tile Avalon® Streaming and Single-Root I/O Virtualization (SR-IOV) IP for PCI Express* User Guide
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Interrupts
8. Registers
9. Testbench and Design Example
10. Troubleshooting and Observing the Link
A. PCI Express Core Architecture
B. TX Credit Adjustment Sample Code
C. Root Port Enumeration
D. Document Revision History

6.1.14. Transaction Layer Configuration Space Interface

The Transaction Layer (TL) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems.
Table 42.  Configuration Space Signals

Signal

Direction

Description

tl_cfg_add[3:0] H-Tile

tl_cfg_add[4:0] L-Tile

Output

Address of the TLP register. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl. Refer to H-Tile Multiplexed Configuration Register Information Available on tl_cfg_ctl or E-Tile Multiplexed Configuration Register Information Available on tl_cfg_ctl for the available information as appropriate.

Address of the TLP register. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl. Refer to L-Tile Multiplexed Configuration Register Information Available on tl_cfg_ctl for the available information.

tl_cfg_ctl[31:0]

Output

The tl_cfg_ctl signal is multiplexed and contains a subset of contents of the Configuration Space registers.

tl_cfg_func[1:0] Output Specifies the function whose Configuration Space register values are being driven tl_cfg_ctl[31:0]. The following encodings are defined:
  • 2'b00: Physical Function (PF0)
  • 2'b01: PF1 for H-Tile, reserved for L-Tile
  • 2'b10: PF2 for H-Tile, reserved for L-Tile
  • 2'b11: PF3 for H-Tile, reserved for L-Tile
app_err_hdr[31:0] Input Header information for the error TLP. Four, 4-byte transfers send this information to the IP core.
app_err_info[10:0] Input The Application can optionally provide the following information:
  • app_err_info[0]: Malformed TLP
  • app_err_info[1]: Receiver Overflow
  • app_err_info[2]: Unexpected Completion
  • app_err_info[3]: Completer Abort
  • app_err_info[4]: Completer Timeout
  • app_err_info[5]: Unsupported Request
  • app_err_info[6]: Poisoned TLP Received
  • app_err_info[7]: AtomicOp Egress Blocked
  • app_err_info[8]: Uncorrectable Internal Error
  • app_err_info[9]: Correctable Internal Error
  • app_err_info[10]: Advisory Non-Fatal Error
app_err_valid Input When asserted, indicates that the data on app_err_info[10:0] is valid. For multi-function variants, the app_err_func_num specifies the function.

Figure 52. Configuration Space Register Access TimingInformation on the Transaction Layer (TL) bus is time-division multiplexed (TDM). When tl_cfg_func[1:0]= 2'b00, tl_cfg_ctl[31:0] drives PF0 Configuration Space register values for eight consecutive cycles. The next 40 cycles are reserved. Then, the 48-cycle pattern repeats.
Table 43.  L-Tile Multiplexed Configuration Register Information Available on tl_cfg_ctl
TDM 31 24 23 16 15 8 7 0
0

[28:24]: Device Number

[29]: Relax order enable

[30]: No snoop enable

[31]: IDO request enable

 Bus Number

[13:8]: Auto negotiation link width

[14]: IDO completion enable

[15]: Memory space enable

Device Control

[2:0]: Max payload size

[5:3]: Max rd req size

[6]: Extended tag enable

[7]: Bus master enable
1

[28:24]AER IRQ Msg num

[29]: cfg_send_corr_err

[30]: cfg_send_nf_err

[31]: cfg_send_f_rr

[16]: RCB cntl

[17]: cfg_pm_no_soft_rst

[23:18]: auto negotiation link width

[12:8]: PCIe cap interrupt msg num

[13]: interrupt disable

[15:14]: Reserved.

[1:0]: Sys power ind. cntl

[3:2]: Sys attention ind cntl

[4]: Sys power cntl

[7:5]: Reserved
2 Index of start VF[6:0] Num VFs

[4:1]: STU

[11:8]: ATS

[15:12]: auto negotiation link speed

[0]: VF enable

[1]: TPH enable

[3:2]: TPH ST mode[1:0]

[4]: Atomic request enable

[5]: ARI forward enable

[6]: ATS cache enable

[7]: ATS STU[0]
3

MSI Address Lower
4

MSI Address Upper
5 MSI Mask
6

MSI Data

 Reserved

[0]: MSI enable

[1]: 64-bit MSI

[4:2]: Multiple MSI enable

[5]: MSI-X enable

[6]: MSI-X func mask
7

Reserved

[5:0]: Auto negotiation link width

[9:6]: Auto negotiation link speed
Table 44.   H-Tile Multiplexed Configuration Register Information Available on tl_cfg_ctl Information on the Transaction Layer (TL) bus is time-division multiplexed (TDM). The TL bus displays the information for each of the 4 PFs and their associated VFs in 10 consecutive cycles. Then, the 40-cycle pattern repeats.
TDM 31 24 23 16 15 8 7 0
0

[28:24]: Device number

[29]: Relaxed Ordering en

[30]: No Snoop en

[31]: (IDO) req en

 Bus Number

[ 8]: unsupported_req_rpt_en

[ 9]: corr_err_rpt_en

[10]: nonfatal_err_rpt_en

[11]: fatal_err_rpt_en

[12]: serr_err

[13]: perr_en

[14]: IDO completion en

[15]: Memory space en

Device Control

[2:0]: Max payload size

[5:3]: Max rd req size

[6]: Extended tag en

[7]: Bus master en
1

Number of VFs[15:0]

[12:8]: PCIe Capability IRQ Msg Num

[13]: IRQ disable

[14]: Rd Cmpl Boundary (RCB) cntl

[15]: pm_no_soft_rst

[1:0]: System ind power cntl

[3:2]: Sys attention ind cntl

[4]: System power cntl

[7:5]: Reserved
2

[16]: Reserved

[27:17]: ]: Index of Start VF[10:0]

[31:28]: Auto negotiation link speed

[8]: ATS cache en

[13:9]: ATS STU[4:0]

[15:14]: Reserved

[0]: VF en

[2:1]: TPH en

[5:3]: TPH ST mode

[6:] Atomic req en

[7]: ARI forward enable
3

MSI Address Lower
4

MSI Address Upper
5 MSI Mask
6

MSI Data

[12:8]: AER IRQ Msg Num

[13]: cfg_send_cor_err

[14]: cfg_send_nf_err

[15]: cfg_send_f_err

[0]: MSI en

[1]: 64-bit MSI

[4:2]: Multiple MSI en

[5]: MSI-X en

[6]: MSI-X func mask

[7]: Reserved
7

AER Uncorrectable Error Mask
8

AER Correctable Error Mask
9

AER Uncorrectable Error Severity
Level Two Title