L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public

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Document Table of Contents

8.1.10.5. Page Size Registers

Table 76.  Supported Page Size Register - 0x1D4

Bits

Register Description

Default Value

Access

[31:0]

Supported Page Sizes. Specifies the page sizes supported by the device

Set in Platform Designer

RO

Table 77.  System Page Size Register - 0x1D8

Bits

Register Description

Default Value

Access

[31:0]

Supported Page Sizes. Specifies the page size currently in use.

Set in Platform Designer

RO