5.4.2. Reset Requirements
The Intel L-/H-Tile Avalon-ST for PCI Express IP Core has two, asynchronous, active low reset inputs, npor and pin_perst. Both reset the Transaction, Data Link and Physical Layers.
The Application Layer drives the npor reset input to the PCIe IP core. If you choose to design an Application Layer does not drive npor, you must tie this output to 1'b1. The npor signal resets all registers and state machines to their initial values.
- NPERSTL0 : Bottom Left PCIe IP core and Configuration via Protocol (CvP)
- NPERSTL1: Middle Left PCIe PCIe IP core (When available)
- NPERSTL2: Top Left PCIe IP core (When available)
- NPERSTR0: Bottom Right PCIe IP core (When available)
- NPERSTR1: Middle Right PCIe IP core (When available)
- NPERSTR2: Top Right PCIe IP core (When available)
When asserted, this signal indicates that the PCIe IP core is in reset. The reset_status signal is synchronous to coreclkout_hip. It is active high.
This signal has the same functionality as reset_status. It is provided for backwards compatibility with Arria® 10 devices. It is active high.
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