L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Document Table of Contents

8.1.2. PCI Configuration Header Registers

The Correspondence between Configuration Space Registers and the PCIe Specification lists the appropriate section of the PCI Express Base Specification that describes these registers.

Figure 61. Configuration Space Registers Address Map
Figure 62. PCI Configuration Space Registers - Byte Address Offsets and Layout

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