L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Document Table of Contents

6.1.8. Clocks

Table 38.  Clocks






This is the input reference clock for the IP core as defined by the PCI Express Card Electromechanical Specification Revision 2.0. The frequency is 100 MHz ±300 ppm. To meet the PCIe* 100 ms wake-up time requirement, this clock must be free-running.

Note: This input reference clock must be stable and free-running at device power-up for a successful device configuration.


This clock drives the Data Link, Transaction, and Application Layers. For the Application Layer, the frequency depends on the data rate and the number of lanes as specified in the table
Data Rate coreclkout_hip Frequency
Gen1 x1, x2, x4, x8, and x16 125 MHz
Gen2 x1, x2, x4, and x8, 125 MHz
Gen2 x16 250 MHz
Gen3 x1, x2, and x4 125 MHz
Gen3 x8 250 MHz

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