L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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Document Table of Contents Avalon-ST TX Interface tx_st_ready Deassertion

This timing diagram illustrates the timing of the TX interface when the Intel L-/H-Tile Avalon-ST for PCI Express IP pauses the application layer by deasserting tx_st_ready. The timing diagram shows a readyLatency of 3 cycles. The application deasserts tx_st_valid after three cycles.
Figure 46. Avalon-ST TX Interface tx_st_ready Deassertion