L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.3.3. Exit from D3 hot

The Power Management Capability register must enable D3Hot PME_Support. In addition, software must set the PME_en bit in the Power Management Control and Status register.