L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide
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3.14. PLL Reconfiguration Interface
This interface is available when you turn on Enable Transceiver dynamic reconfiguration on the Configuration, Debug and Extension Options tab using the parameter editor.
To ensure proper system operation, reset or repeat device enumeration of the PCIe* link after changing the value of read-only PLL registers.