L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public
Document Table of Contents

6.1.10. Function-Level Reset (FLR) Interface

The function-level reset (FLR) interface can reset the individual SR-IOV functions.

Table 39.  Function-Level Reset (FLR) Interface

Signal

Direction

Description

flr_pf_active[<n>-1:0]H-Tile

Output

The SR-IOV Bridge asserts flr_pf_active when bit 15 of the PCIe Device Control Register is set. Bit 15 is the FLR field. Once asserted, the flr_pf_active signal remains high until the Application Layer sets flr_pf_done high for the associated function.

The Application Layer must perform actions necessary to clear any pending transactions associated with the function being reset. The Application Layer must assert flr_pf_done to indicate it has completed the FLR actions and is ready to re-enable the PF.

flr_pf_done[<n>-1:0]H-Tile

Input

<n> is the number of PFs.

When asserted for one or more cycles, indicates that the Application Layer has completed resetting all the logic associated with the PF. Bit 0 is for PF0. Bit 1 is for PF1, and so on. Users decode the FLR write to PF register through the cfg write broadcast bus to know the PF should be FLR-ed. When flr_pf_active is asserted, the Application Layer must assert flr_completed within 100 milliseconds to re-enable the function.

flr_rcvd_vf

H-Tile
Output

The SR-IOV Bridge asserts this output port for one cycle when a 1 is being written into the PCIe Device Control Register FLR field, bit[15], of the of a VF. flr_rcvd_pf_num and flr_rcvd_vf_num drive PF number and the VF offset associated with the Function being reset.

The Application Layer responds to a pulse on this output by clearing any pending transactions associated with the VF being reset. It then asserts flr_completed_vf to indicate that it has completed the FLR actions and is ready to re-enable the VF.

flr_rcvd_pf_num[<n>-1:0] H-Tile

Output When flr_rcvd_vf is asserted, this output specifies the PF number associated with the VF being reset.

<n> is the PF number.

flr_rcvd_vf_num[log2 <n>-1:0] H-Tile

Output

When flr_rcvd_vf is asserted, this output specifies the VF number offset associated with the VF being reset.

<n> is the number of VFs.

flr_completed_vfH-Tile

Input

When asserted, indicates that the Application Layer has completed resetting all the logic associated with flr_completed_vf_num[<n>-1:0].

When flr_active_vf<n> asserts, the Application Layer it must assert the corresponding bit of flr_completed_vf within 100 milliseconds to re-enable the VF.

<n> is the total number of VFs.

flr_completed_pf_num[<n>-1:0]

H-Tile
Input When flr_completed_vf is asserted, this input specifies the PF number associated with the VF that has completed .

<n> is the number of PFs.

flr_completed_vf_num[log2 <n>-1:0]H-Tile Input When flr_completed_vf is asserted, this input specifies the VF number associated with the VF that has completed its FLR.

<n> is the total number of VFs.

Figure 49. FLR Interface Timing Diagram for Physical Functions
Figure 50. FLR Interface Timing Diagram for Virtual Functions

Did you find the information on this page useful?

Characters remaining:

Feedback Message