L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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Document Table of Contents

4.6.1. Device Capabilities

Table 18.  Device Registers


Possible Values

Default Value



Maximum payload sizes supported

128 bytes

256 bytes

512 bytes

1024 bytes

512 bytes


Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities register.

PF0 Support extended tag field





When you turn this option On, the core supports 256 tags, improving the performance of high latency systems. Turning this option on turns on the Extended Tag bit in the Configuration Space Device Capabilities register.

The IP core tracks tags for Non-Posted Requests. The tracking clears when the IP core receives the last Completion TLP for a MemRd.