L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Document Table of Contents

6.3.2. End Point D3 Exit

An End Point can exit the D3 state if the following two conditions are true: First, the PME_Support setting in the Power Management Capabilities (PMC) register must enable PME notification. Second, software must set the PME_en bit in the Power Management Control and Status (PMCSR) register.

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