L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022

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Document Table of Contents

4.1. Stratix 10 Avalon-ST Settings

Table 12.  System Settings for PCI Express




Enable Avalon-ST reset output port On/Off

When On, the generated reset output port clr_st has the same functionality as the hip_ready_n port included in the Hard IP Reset interface. This option is available for backwards compatibility with Arria® 10 devices.

Enable byte parity ports on Avalon-ST interface


When On, the RX and TX datapaths are parity protected. Parity is even. The Application Layer must provide valid byte parity in the Avalon-ST TX direction.

This parameter is only available for the Intel L-/H-Tile Avalon-ST for PCI Express IP.