Visible to Intel only — GUID: lbl1466722478760
Ixiasoft
Visible to Intel only — GUID: lbl1466722478760
Ixiasoft
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces
The ordering of bytes in the header and data portions of packets is different. The first byte of the header dword is located in the most significant byte of the dword. The first byte of the data dword is located in the least significant byte of the dword on the data bus.
Packet | TLP |
---|---|
Header0 | pcie_hdr_byte0, pcie_hdr_byte1, pcie_hdr_byte2, pcie_hdr_byte3 |
Header1 | pcie_hdr_byte4, pcie_hdr_byte5, pcie_hdr_byte6, pcie_hdr_byte7 |
Header2 | pcie_hdr_byte8, pcie_hdr_byte9, pcie_hdr_byte10, pcie_hdr_byte11 |
Header3 | pcie_hdr_byte12, pcie_hdr_byte13, pcie_hdr_byte14, pcie_hdr_byte15 |
Data0 | pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0 |
Data1 | pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4 |
Data2 | pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8 |
Data<n> | pcie_data_byte<4n+3>, pcie_data_byte<4n+2>, pcie_data_byte<4n+1>, pcie_data_byte0<4n> |
The following figure illustrates the mapping of Avalon-ST packets to PCI Express* TLPs for a three-dword header and a four-dword header. In the figure, H0 to H3 are header dwords, and D0 to D9 are data dwords.
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