Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Document Table of Contents

3.1.3. The AVST_READY Signal

Before beginning configuration, trigger device cleaning by toggling the nCONFIG pin from high to low to high. This nCONFIG transition also returns the device to the configuration state.

If you use the Parallel Flash Loader II Intel® FPGA IP core as the configuration host, the AVST_READY synchronizer logic is included.

Figure 16. Monitoring the AVST_READY Signal and Responding to Backpressure

The configuration files for Intel® Stratix® 10 devices can be highly compressed. During configuration, the decompression of the bit stream inside the device requires the host to pause before sending more data. The Intel® Stratix® 10 device asserts the AVST_READY signal when the device is ready to accept data. The AVST_READY signal is only valid when the nSTATUS pin is high. In addition, the host must handle backpressure by monitoring the AVST_READY signal and may assert AVST_VALID signal any time after the assertion of AVST_READY signal. The host must monitor the AVST_READY signal throughout the configuration.

The AVST_READY signal sent by the Intel® Stratix® 10 device to the host is not synchronized with the AVSTx8_CLK or AVST_CLK. To configure the Intel® Stratix® 10 device successfully, the host must adhere to the following constraints:

  • The host must drive no more than six data words after the deassertion of the AVST_READY signal including the delay incurred by the 2-stage register synchronizer.
  • The host must synchronize the AVST_READY signal to the AVST_CLK signal using a 2-stage register synchronizer. Here is Register transfer level (RTL) example code for 2-stage register synchronizer:
    always @(posedge avst_clk or negedge reset_n) 
    		if (~reset_n)
    			fpga_avst_ready_reg1 <= 0;
    			fpga_avst_ready_reg2 <= 0;
    			fpga_avst_ready_reg1 <= fpga_avst_ready;
    			fpga_avst_ready_reg2 <= fpga_avst_ready_reg1;
    • The AVST_CLK signal comes from either PFL II IP or your Avalon® -ST controller logic.
    • fpga_avst_ready is the AVST_READY signal from the Intel® Stratix® 10 device.
    • fpga_avst_ready_reg2 signal is the AVST_READY signal that is synchronous to AVST_CLK.
Note: You must properly constrain the AVST_CLK and AVST_DATA signals at the host. Perform timing analysis on both signals between the host and Intel® Stratix® 10 device to ensure the Avalon-ST configuration timing specifications are met. Refer to the Avalon-ST Configuration Timing section of the Intel® Stratix® 10 Device Data Sheet for information about the timing specifications.
Note: The AVST_CLK signal must run continuously during configuration. The AVST_READY signal will not assert unless the clock is running.

Optionally, you can monitor the CONF_DONE signal to indicate the flash has sent all the data to FPGA or to indicate the configuration process is complete.

If you use the PFL II IP core as the configuration host, you can use the Intel® Quartus® Prime software to store the binary configuration data to the flash memory through the PFL II IP core.

If you use the Avalon-ST Adapter IP core as part of the configuration host, set the Source Ready Latency value between 1- 6.

Avalon-ST x8 configuration scheme uses the SDM pins only. Avalon-ST x16 and x32 configuration scheme only use dual-purpose I/O pins that you can use as general-purpose I/O pins after configuration.

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