Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.1.7.1.1. Generating and Programming a .pof into CFI Flash

The Intel® Quartus® Prime software generates the .sof when you compile your design. You use the .sof to generate the .pof. This process includes the following steps:

  1. Generating a .pof for the PFL II IP using the Intel® Quartus® Prime File > Programming File Generator.
  2. Using the Intel® Quartus® Prime Programmer to write the Intel® Stratix® 10 device .pof to the flash device.
Figure 20. Programming the CFI Flash Memory with the JTAG Interface

The PFL II IP core supports dual flash memory devices in burst read mode to achieve faster configuration times. You can connect two MT28EW CFI flash memory devices to the host in parallel using the same data bus, clock, and control signals. Intel does not support connecting two of non-MT28W CFI flash memory devices to PFL II IP core in parallel. During FPGA configuration, the AVST_CLK frequency is four times faster than the flash_clk frequency.

Figure 21. PFL II IP core with Dual MT28EW CFI Flash Memory DevicesThe flash memory devices must have the same memory density from the same device family and manufacturer.

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