Intel® Stratix® 10 Configuration User Guide

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ID 683762
Date 5/30/2022
Public
Document Table of Contents

5.3. Commands and Responses

The host controller communicates with the SDM using command and response packets via the Mailbox Client Intel® FPGA IP.

The first word of the command and response packets is a header that provides basic information about the command or response.

Block Diagram

The following figure illustrates the role of the Mailbox Client Intel® FPGA IP in a Intel® Stratix® 10 design. The Mailbox Client IP enables communication with the SDM to access quad SPI flash memory and system status.

Mailbox Client Role

Figure 67. Command and Response Header Format
Note: The LENGTH field in the command header must match the command length of corresponding command. Your client must read all the response words, even if your client does not interpret all the response words.

The following table describes the fields of the header command.

Table 37.  Command and Response Header Description
Header Bit Description
Reserved [31:28] Reserved.
ID [27:24] The command ID. The response header returns the ID specified in the command header. Refer to Operation Commands for command descriptions.
0 [23] Reserved.
LENGTH [22:12] Number of words of arguments following the header. The IP responds with an error if a wrong number of words of arguments is entered for a given command.
Reserved [11] Reserved. Must be set to 0.
Command Code/Error Code [10:0] Command Code specifies the command. The Error Code indicates whether the command succeeded or failed.

In the command header, these bits represent command code. In the response header, these bits represent error code. If the command succeeds, the Error Code is 0. If the command fails, refer to the error codes defined in the Error Code Responses.

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