Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

5.6.1. Prerequisites

To run this remote system update example, your system must meet the following hardware and software requirements:
  • You should be running the Intel® Quartus® Prime Pro Edition software version 19.1 or later.
  • You should create and download this example to the Intel® Stratix® 10 SoC Development Kit.
  • Your design should include the Mailbox Client Intel® FPGA IP that connects to a JTAG to Avalon® Master Bridge as shown the Platform Designer system. The JTAG to Avalon® Master Bridge acts as the remote system update host controller for your factory and application images.
  • In addition, your design must include the Reset Release Intel® FPGA IP. This component holds the design in reset until the entire FPGA fabric has entered user mode.
  • The ninit_done_reset and reset_bridge_1 components create a two-stage reset synchronizer to release the Mailbox Client Intel® FPGA IP and JTAG to Avalon Master Bridge Intel® FPGA IP from reset when the device configuration is complete and the device is in user mode.
  • The ninit_done output signal from Reset Release IP gates this reset by connecting to the ninit_done_reset in_reset pin.
  • The reset_in Reset Bridge Intel® FPGA IP provides a user mode reset. In this design, the exported resetpin connects to application logic.
  • Figure 75. Required Communication and Host Components for the Remote System Update Design Example

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