Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 10/21/2022
Public
Document Table of Contents

3.2.5.2. Maximum Allowable External nCSO Pin Skew Delay Guidelines

Use the following equations to determine the skew between nCSO and AS_CLK:

  1. Skew (Tbd_clk – Tbd_ncso) > Tsu_ncso – Tdcsfrs
  2. Skew (Tbd_clk – Tbd_ncso) < AS_CLK/2 + Tdcslst – Tho_ncso

Hence, the allowable range for skew between nCSO and AS_CLK is as follows:

Tsu_ncso - Tdcsfrs < Skew (Tbd_clk – Tbd_ncso) < AS_CLK/2 + Tdcslst - Tho_ncso

  • Tsu_ncso = Chip select setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tho_ncso = Chip select hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tdcsfrs = AS_nCSO[3:0] asserted to first AS_CLK edge. Refer to the AS configuration timing specifications in the Intel® Stratix® 10 Device Data Sheet.
  • Tdcslst = Last AS_CLK edge to AS_nCSO[3:0] deasserted. Refer to the AS configuration timing specifications in the Intel® Stratix® 10 Device Data Sheet.
  • AS_CLK = AS_CLK clock period.

Example to Determine the Skew for 1 GB Quad SPI Flash Devices

Tsu_ncso = 2.7 ns

Tho_ncso = 3.375 ns

Tdcsfrs = 11.65 ns

Tdcslst = 9.23 ns

AS_CLK = 8 ns (125 MHz)

  1. Skew (Tbd_clk – Tbd_ncso) > Tsu_ncso – Tdcsfrs

    Skew (Tbd_clk – Tbd_ncso) > 2.7 – 11.65

    Skew (Tbd_clk – Tbd_ncso) > –8.95 ns

  2. Skew (Tbd_clk – Tbd_ncso) < AS_CLK/2 + Tdcslst – Tho_ncso

    Skew (Tbd_clk – Tbd_ncso) < 8/2 + 9.23 – 3.375

    Skew (Tbd_clk – Tbd_ncso) < 9.855 ns

The allowable range for skew between nCSO and AS_CLK is -8.95 ns < Skew (Tbd_clk – Tbd_ncso) < 9.855 ns

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