Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

2.5.2. MSEL Settings

After power-on MSEL[2:0] pins specify the configuration scheme for Intel® Stratix® 10 devices. Use 4.7-kΩ resistors to pull the MSEL[2:0] pins up to VCCIO_SDM or down to ground as required by the MSEL[2:0] setting for your configuration scheme.

Figure 8. MSEL Pull-Up and Pull-Down Circuit Diagram
Table 7.  MSEL Settings for Each Configuration Scheme of Intel® Stratix® 10 Devices
Configuration Scheme MSEL[2:0]
Avalon-ST (x32) 000
Avalon-ST (x16) 101
Avalon-ST (x8) 110
AS (Fast mode – for CvP) 5 001
AS (Normal mode) 6 011
JTAG only7 111
You must also specify the configuration scheme on the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime Software.
Figure 9. Specify Configuration Scheme to Specify MSEL Value
5 If you use AS Fast mode, you must ramp all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel® Stratix® 10 device begins to access it.
6 If you use AS Normal mode, you must fully ramp the VCCIO_SDM supply to the recommended operating condition within 10 ms.
7 JTAG configuration works with any valid MSEL settings, unless disabled for security.

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