Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

7.5. Configuration Pin Differences from Previous Device Families

Intel® Stratix® 10 configuration pin behavior is different from earlier device families. Knowing about these differences and how these pins behave can help you understand and debug configuration issues.

Configuration Pin Names (Pre- Intel® Stratix® 10) Intel® Stratix® 10 Pin Names Notes

TRST

Not Available

Use the TMS reset sequence. Hold TMS high for 5 TCK cycles.

CLKUSR

OSC_CLK_1

An external source you can supply to increase the configuration throughput to 250 MHz. Using an external clock source Transceivers, the HPS, PCIe* , and the High Bandwidth Memory (HBM2) require this external clock.

  • 25
  • 100
  • 125

Refer to Setting Configuration Clock Source for instructions on setting the clock source and frequency in the Intel® Quartus® Prime Pro Edition software.

CRC_ERROR

Any unused SDM_IO (SEU_ERROR)

No dedicated location. Now called SEU_ERROR. Ignore until after CONF_DONE asserts.

CONF_DONE

SDM_IO5, SDM_IO16 (CONF_DONE)

No single dedicated pin location. No longer Open Drain. External pull-up is not mandatory.

DCLK (PS - FPP)

AVST_CLK, AVSTx8_CLK

x8 mode has a dedicated clock input on SDM_IO14 (AVSTx8_CLK). For other Avalon® -ST modes, use AVST_CLK.

AVST_CLK and AVSTx8_CLK must be continuous and cannot pause during configuration.

DCLK (AS)

SDM_IO2 (AS_CLK)

When using the internal oscillator in AS mode, the AS_CLK runs in the range of 57 - 115 based on AS_CLK selection. If you provide a 25 MHz, 100 MHz or 125 MHz clock to the OSC_CLK_1 pin, the AS_CLK can run up to 125 MHz.

DEV_OE

Not Available

DEV_CLRn

Not Available

INIT_DONE

SDM_IO0

SDM_IO16

INIT_DONE

No longer Open Drain.

MSEL[0]

SDM_IO5 (MSEL[0])

After the SDM samples MSEL this pin functions as per the configuration mode selected. Do not connect directly to power. Use 4.7 KΩ pull-up or pull-downs, as appropriate.

MSEL[1]

SDM_IO7 (MSEL[1])

After the SDM samples MSEL, this pin functions as per the configuration mode selected. Do not connect directly to power. Use 4.7 KΩ pull-up or pull-downs, as appropriate.

MSEL[2]

SDM_IO9 (MSEL[2])

After the SDM samples MSEL, this pin functions as per the configuration mode selected. Do not connect directly to power. Use 4.7 KΩ pull-up or pull-downs, as appropriate.

NSTATUS

nSTATUS

No longer Open Drain. Intel recommends a 10 KΩ pull-up to VCCIO_SDM.

NCE

Not Available

Multi-device configuration is not supported.

NCEO

Not Available

Multi-device configuration is not supported.

DATA[31:0] (PP32/PP16)

AVST_DATA[31:0]

Avalon® -ST x8 uses SDM pins for data pins.

DATA[7:0] (PP8)

SDM _IO pins (AVSTx8_DATAn)

nCSO[2:0]

SDM_IO8 (AS_nCSO3)

SDM_IO7 (AS_nCSO2)SDM_IO9 (AS_nCSO1) SDM_IO5 (AS_nCSO0)

Intel® Stratix® 10 supports up to 4 cascaded AS devices

nIO_PULLUP

Not Available

Use a JTAG instruction to invoke.

AS_DATA0_ASDO

SDM_IO4 (AS_DATA0)

AS_DATA[3:1]

SDM_IO6 (AS_DATA3)

SDM_IO3 (AS_DATA2)

SDM_IO1 (AS_DATA1)

Unlike earlier device families, the AS interface does not automatically tristate at power-on. When you set MSEL to JTAG, the SDM drives the AS_CLK, AS_DATA0-AS_DATA3, and AS_nCSO0-AS_nCSO3, MSEL pins until POR.

PR_REQUEST

GPIO*

No dedicated location.

PR_READY

GPIO*

No dedicated location.

PR_ERROR

GPIO*

No dedicated location.

PR_DONE

GPIO*

No dedicated location.

CVP_CONFDONE

Any unused SDM_IO CVP_CONFDONE

Did you find the information on this page useful?

Characters remaining:

Feedback Message