Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

2.7. Maximum Configuration Time Estimation

Hyper Initialization is an option that can be enabled or disabled through the setting in the Intel® Quartus® Prime software to initialize or reset the Intel® Hyperflex™ registers to a known state at device configuration. By default, this option is off. For information about register initialization, refer to Device Initialization. For more information about Intel® Hyperflex™ registers, refer to the Intel® Hyperflex™ Architecture High-Performance Design Handbook.

The configuration time is the time estimated for the entire configuration state. For more information, refer to Power-On, Configuration, and Reconfiguration Timing Diagram.

The maximum configuration time is estimated when the device starts configuration until CONF_DONE is asserted to high.

Table 10.  Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices ( Avalon® -ST)
Note: Provided configuration times are based on the AVST_CLK = 125 MHz.
Variant Product Line Maximum Configuration Time (ms) [Hyper Initialization Off/Hyper Initialization On]
AVST ×8 9 AVST ×16 9 AVST ×32 9
Configuration Clock Source: Internal Oscillator Configuration Clock Source: OSC_CLK_1 (25/100/125 MHz) Configuration Clock Source: Internal Oscillator Configuration Clock Source: OSC_CLK_1 (25/100/125 MHz) Configuration Clock Source: Internal Oscillator Configuration Clock Source: OSC_CLK_1 (25/100/125 MHz)
Intel® Stratix® 10 GX, SX, TX, MX, and DX GX 400, SX 400, TX 400 183/222 122/148 108/147 72/98 90/129 60/86
GX 650, SX 650 274/334 182/222 154/216 102/144 120/184 80/122
GX 850, GX 1100, SX 850, SX 1100, TX 850, TX 1100, DX 1100 456/1,200 304/378 246/358 164/238 190/300 126/200
GX 1660, GX 2110, TX 1650, TX 2100, MX 1650, MX 2100, DX 2100 754/852 502/568 394/496 262/330 214/316 142/210
GX 1650, GX 2100, GX 2500, GX 2800, SX 1650, SX 2100, SX 2500, SX 2800, TX 2500, TX 2800, DX 2800 1,102/1,240 734/826 568/708 378/472 300/442 200/294
GX 10M 10 1,446/1,662 964/1,108 N/A N/A N/A N/A
Table 11.  Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices (AS x4)
Note: Provided configuration times are based on the AS_CLK = 115 MHz for Internal Oscillator and AS_CLK = 125 MHz for OSC_CLK_1 (25/100/125 MHz).
Variant Product Line Maximum Configuration Time (ms) [Hyper Initialization Off/Hyper Initialization On]
AS ×4
Configuration Clock Source: Internal Oscillator Configuration Clock Source: OSC_CLK_1 (25/100/125 MHz)
Intel® Stratix® 10 GX, SX, TX, MX, and DX GX 400, SX 400, TX 400 408/447 272/298
GX 650, SX 650 568/630 378/420
GX 850, GX 1100, SX 850, SX 1100, TX 850, TX 1100, DX 1100 900/1,012 600/674
GX 1660, GX 2110, TX 1650, TX 2100, MX 1650, MX 2100, DX 2100 1,432/1,534 954/1,022
GX 1650, GX 2100, GX 2500, GX 2800, SX 1650, SX 2100, SX 2500, SX 2800, TX 2500, TX 2800, DX 2800 2,058/2,200 1,372/1,466
9 The maximum configuration time does not include the time incurred from external storage and control logic, and transceiver calibration time.
10 Intel® Stratix® 10 GX 10M FPGA has two high-density Intel® Stratix® 10 GX FPGA core fabric dies. The values estimate configuration time for one core fabric die.

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