Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.2.8. AS_CLK

The Intel® Stratix® 10 device drives AS_CLK to the serial flash device. An internal oscillator or the external clock that drives the OSC_CLK_1 pin generates AS_CLK. Using an external clock source allows the AS_CLK to run at a higher frequency. If you provide a 25 MHz, 100 MHz, or 125 MHz clock to the OSC_CLK_1 pin, the AS_CLK can run up to 125 MHz .

Set the maximum required frequency for the AS_CLK pin in the Intel® Quartus® Prime software as described in Active Serial Configuration Software Settings. The AS_CLK pin runs at or below your selected frequency.

Table 33.  Supported Configuration Clock Source and AS_CLK Frequencies in Intel® Stratix® 10 DevicesThe table displays valid AS_CLK settings for the respective configuration clock source.
Configuration Clock Source AS_CLK Frequency (MHz)
Internal oscillator

25

58

77

115

OSC_CLK_1 (25/100/125 MHz)

25

50

71.5

100 14

125 15

Note: The configuration fails if the firmware receives bitstream with an invalid AS_CLK setting. For firmware in Intel® Quartus® Prime software version before 21.1, if AS_CLK is set incorrectly, the firmware defaults the AS_CLK frequency to 50 MHz to complete the AS x4 configuration.
14 The .sof files, generated with selected 108 MHz AS_CLK frequency in the earlier versions of Intel® Quartus® Prime software, default to this frequency when you generate a programming file (.jic/.pof/.rbf/.rpd) using Intel® Quartus® Prime Programming File Generator version 21.1 or newer.
15 The .sof files, generated with selected 133 MHz AS_CLK frequency in the earlier versions of Intel® Quartus® Prime software, default to this frequency when you generate a programming file (.jic/.pof/.rbf/.rpd) using Intel® Quartus® Prime Programming File Generator version 21.1 or newer.

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