- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
2.6.2. OSC_CLK_1 Clock Input
When you drive the OSC_CLK_1 input clock with an external clock source and enable OSC_CLK_1 in the Intel® Quartus® Prime software, the device loads the majority of the configuration bitstream at 250 MHz. Intel® Stratix® 10 devices include an internal oscillator in addition to OSC_CLK_1 which runs the configuration process at a frequency between 170-230 MHz . Intel® Stratix® 10 devices always use this internal oscillator to load the first section of the bitstream, up to a maximum of 256 kilobyte (KB). The SDM can use either clock source for the remainder of device configuration. If you use the internal oscillator, you can leave the OSC_CLK_1 unconnected. If you use transceivers, you must provide an external clock to this pin.
When you specify OSC_CLK_1 for configuration, the OSC_CLK_1 clock must be a stable and free-running clock.
When you specify AS configuration scheme and nCONFIG is pull high, the SDM starts the configuration once the device exits the POR state. Ensure the OSC_CLK_1 clock is available before SDM starts to load the bitstream from the quad SPI flash or you need to supply a stable free-running clock before/at the same time VCCIO_SDM ramps up to the typical voltage level.
Device configuration may fail under the following conditions when you select the OSC_CLK_1 as the clock source for configuration:
- You fail to drive the OSC_CLK_1 pin or the OSC_CLK_1 is not stable and free running due to an interruption or a frequency change.
- You drive the OSC_CLK_1 pin at an incorrect frequency. Select one of the following input reference clock frequencies to drive the OSC_CLK_1 pin:
- 25 MHz
- 100 MHz
- 125 MHz
The Intel® Stratix® 10 device multiplies the OSC_CLK_1 source clock frequency to generate a 250 MHz clock for configuration. Using an OSC_CLK_1 source enables the fastest possible configuration. Refer to Setting Configuration Clock Source for instructions setting this frequency using the Intel® Quartus® Prime Software.
Configuration Clock Requirements for Reconfiguration Without Power Cycling the Device
When you specify OSC_CLK_1 for configuration and reconfigure without powering down the Intel® Stratix® 10 device, the device can only reconfigure with OSC_CLK_1. In this scenario, OSC_CLK_1 must be a free-running clock.
Configuration Clock Requirements for Configuration After Powering Cycling the Device
After a power-down, when you specify OSC_CLK_1 for configuration, the Intel® Stratix® 10 device uses the internal oscillator to load the first section of the bitstream and OSC_CLK_1 for the remainder.
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