188.8.131.52.1. PFL II Parameters
|What operating mode will be used?||
||Specifies the operating mode of flash programming and FPGA configuration control in one IP core or separate these functions into individual blocks and functionality.|
|What is the targeted flash?||
||Specifies the flash memory device connected to the PFL II IP core.|
|Set flash bus pins to tri-state when not in use||
||Allows the PFL II IP core to tri-state all pins interfacing with the flash memory device when the PFL II IP core does not require access to the flash memory.|
|How many flash devices will be used?||
||Specifies the number of flash memory devices connected to the PFL II IP core.|
|What's the largest flash device that will be used?||
Specifies the density of the flash memory device to be programmed or used for FPGA configuration. If you have more than one flash memory device connected to the PFL II IP core, specify the largest flash memory device density.
For dual CFI flash, select the density that is equivalent to the sum of the density of two flash memories. For example, if you use two 512-Mb CFI flashes, you must select CFI 1 Gbit.
|What is the flash interface data width||
Specifies the flash data width in bits. The flash data width depends on the flash memory device you use. For multiple flash memory device support, the data width must be the same for all connected flash memory devices.
Select the flash data width that is equivalent to the sum of the data width of two flash memories. For example, if you are targeting dual solution, you must select 32 bits because each CFI flash data width is 16 bits.
|Allow user to control FLASH_NRESET pin||
Creates a FLASH_NRESET pin in the PFL II IP core to connect to the reset pin of the flash memory device. A low signal resets the flash memory device. In burst mode, this pin is available by default.
When using a Cypress GL flash memory, connect this pin to the RESET pin of the flash memory.
|Flash programming IP optimization target||
||Specifies the flash programming IP optimization. If you optimize the PFL II IP core for Speed, the flash programming time is shorter, but the IP core uses more LEs. If you optimize the PFL II IP core for Area, the IP core uses fewer LEs, but the flash programming time is longer.|
|Flash programming IP FIFO size||
||Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL II IP core uses additional LEs to implement FIFO as temporary storage for programming data during flash programming. With a larger FIFO size, programming time is shorter.|
|Add Block-CRC verification acceleration support||
||Adds a block to accelerate verification.|
|What is the external clock frequency?||Provide the frequency of your external clock.||Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The clock frequency must not exceed two times the maximum clock (AVST_CLK) frequency the FPGA can use for configuration. The PFL II IP core can divide the frequency of the input clock maximum by two.|
|What is the flash access time?||Provide the access time from the flash data sheet.||
Specifies the flash access time. This information is available from the flash datasheet. Intel recommends specifying a flash access time that is equal to or greater than the required time.
For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses pages instead of bytes and requires greater access time. This option is disabled for quad SPI flash.
|What is the byte address of the option bits, in hex?||Provide the byte address of the option bits.||
Specifies the option bits start address in flash memory. The start address must reside on an 8 KB boundary. This address must be the same as the bit sector address you specified when converting the .sof to a .pof.
For more information refer to Storing Option Bits.
|Which FPGA configuration scheme will be used?||
||Specifies the width of the Avalon® -ST interface.|
|What should occur on configuration failure?||
||Configuration behavior after configuration failure.
|What is the byte address to retry from failure||—||If you select Retry from fixed address for configuration failure option, this option specifies the flash address the PFL II IP core to reads from.|
|Include input to force reconfiguration||
||Includes the optional pfl_nreconfigure reconfiguration input pin to enable reconfiguration of the FPGA.|
|Enable watchdog timer on Remote System Update support||
||Enables a watchdog timer for remote system update support. Turning on this option enables the pfl_reset_watchdog input pin and pfl_watchdog_error output pin. This option also specifies the period before the watchdog timer times out. The watchdog timer runs at the pfl_clk frequency.|
|Time period before the watchdog timer times out||—||Specifies the time out period for the watchdog timer. The default time out period is 100 ms.|
|Use advance read mode?||
||This option improves the overall flash access time for the read process during the FPGA configuration.
||Specifies the latency count for Intel Burst mode.|
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