Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.1.7.2.1. PFL II Parameters

Table 21.  PFL II General Parameters
Options Value Description
What operating mode will be used?
  • Flash Programming
  • FPGA Configuration
  • Flash Programming and FPGA Configuration
Specifies the operating mode of flash programming and FPGA configuration control in one IP core or separate these functions into individual blocks and functionality.
What is the targeted flash?
  • CFI Parallel Flash
  • Quad SPI Flash
Specifies the flash memory device connected to the PFL II IP core.
Set flash bus pins to tri-state when not in use
  • On
  • Off
Allows the PFL II IP core to tri-state all pins interfacing with the flash memory device when the PFL II IP core does not require access to the flash memory.
Table 22.  PFL II Flash Interface Setting Parameters
Options Value Description
How many flash devices will be used?
  • 1–16
Specifies the number of flash memory devices connected to the PFL II IP core.
What's the largest flash device that will be used?
  • 8 Mbit–4 Gbit

Specifies the density of the flash memory device to be programmed or used for FPGA configuration. If you have more than one flash memory device connected to the PFL II IP core, specify the largest flash memory device density.

For dual CFI flash, select the density that is equivalent to the sum of the density of two flash memories. For example, if you use two 512-Mb CFI flashes, you must select CFI 1 Gbit.

What is the flash interface data width
  • 8
  • 16
  • 32

Specifies the flash data width in bits. The flash data width depends on the flash memory device you use. For multiple flash memory device support, the data width must be the same for all connected flash memory devices.

Select the flash data width that is equivalent to the sum of the data width of two flash memories. For example, if you are targeting dual solution, you must select 32 bits because each CFI flash data width is 16 bits.

Allow user to control FLASH_NRESET pin
  • On
  • Off

Creates a FLASH_NRESET pin in the PFL II IP core to connect to the reset pin of the flash memory device. A low signal resets the flash memory device. In burst mode, this pin is available by default.

When using a Cypress GL flash memory, connect this pin to the RESET pin of the flash memory.

Table 23.  PFL II Flash Programming Parameters
Options Value Description
Flash programming IP optimization target
  • Area
  • Speed
Specifies the flash programming IP optimization. If you optimize the PFL II IP core for Speed, the flash programming time is shorter, but the IP core uses more LEs. If you optimize the PFL II IP core for Area, the IP core uses fewer LEs, but the flash programming time is longer.
Flash programming IP FIFO size
  • 16
  • 32
Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL II IP core uses additional LEs to implement FIFO as temporary storage for programming data during flash programming. With a larger FIFO size, programming time is shorter.
Add Block-CRC verification acceleration support
  • On
  • Off
Adds a block to accelerate verification.
Table 24.  PFL II FPGA Configuration Parameters
Options Value Description
What is the external clock frequency? Provide the frequency of your external clock. Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The clock frequency must not exceed two times the maximum clock (AVST_CLK) frequency the FPGA can use for configuration. The PFL II IP core can divide the frequency of the input clock maximum by two.
What is the flash access time? Provide the access time from the flash data sheet.

Specifies the flash access time. This information is available from the flash datasheet. Intel recommends specifying a flash access time that is equal to or greater than the required time.

For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses pages instead of bytes and requires greater access time. This option is disabled for quad SPI flash.

What is the byte address of the option bits, in hex? Provide the byte address of the option bits.

Specifies the option bits start address in flash memory. The start address must reside on an 8 KB boundary. This address must be the same as the bit sector address you specified when converting the .sof to a .pof.

For more information refer to Storing Option Bits.

Which FPGA configuration scheme will be used?
  • Avalon® -ST x8
  • Avalon® -ST x16
  • Avalon® -ST x32
Specifies the width of the Avalon® -ST interface.
What should occur on configuration failure?
  • Halt
  • Retry same page
  • Retry from fixed address
Configuration behavior after configuration failure.
  • If you select Halt, the FPGA configuration stops completely after failure.
  • If you select Retry same page, after failure, the PFL II IP core reconfigures the FPGA with data from the page that failed.
  • If you select Retry from fixed address, the PFL II IP core reconfigures the FPGA a fixed address.
What is the byte address to retry from failure If you select Retry from fixed address for configuration failure option, this option specifies the flash address the PFL II IP core to reads from.
Include input to force reconfiguration
  • On
  • Off
Includes the optional pfl_nreconfigure reconfiguration input pin to enable reconfiguration of the FPGA.
Enable watchdog timer on Remote System Update support
  • On
  • Off
Enables a watchdog timer for remote system update support. Turning on this option enables the pfl_reset_watchdog input pin and pfl_watchdog_error output pin. This option also specifies the period before the watchdog timer times out. The watchdog timer runs at the pfl_clk frequency.
Time period before the watchdog timer times out Specifies the time out period for the watchdog timer. The default time out period is 100 ms.
Use advance read mode?
  • Normal mode
  • Intel Burst mode
  • 16 byte page mode (GL only)
  • 32 byte page mode (MT28EW)
  • Micron Burst Mode (M58BW)
This option improves the overall flash access time for the read process during the FPGA configuration.
  • Normal mode—applicable for all flash memory
  • Intel Burst mode—Applicable for devices that support bursting. Reduces sequential read access time
  • 16 byte page mode (GL only)—applicable for Cypress GL flash memory only
  • 32 byte page mode (MT28EW)—applicable tor MT28EW only
  • Micron Burst Mode (M58BW)—applicable for Micron M58BW flash memory only
For more information about the read-access modes of the flash memory device, refer to the respective flash memory data sheet.
Latency count
  • 3
  • 4
  • 5
Specifies the latency count for Intel Burst mode.

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